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S3C72K8/p72k8 product overview 1- 1 1 product overview overview the S3C72K8 singl-chip cmos microcontroller has been designed for high performance using samsung's newest 4-bit cpu core, sam48 ( samsung arrageable microcontrollers). with a two-channel comparator, up-to- 320-dot lcd direct drive capability, 8-bit timer/counter, watchdog timer and serial i/o, the S3C72K8 offers an excellent design solution for a wide variety of applications which require lcd functions. up to 27 pins of the 80-pin qfp package can be dedicated to i/o. seven vectored interrupts provide fast response to internal and external events. in addition, the S3C72K8's advanced cmos technology provides for low power consumption and a wide operating voltage range. otp the S3C72K8 microcontroller is also available is otp (one time programmable) version, s3p72k8. s3p72k8 microcontroller has an one-chop 8 kbyte one time programmable eprom instead of masked rom. the s3p72k8 is comparable to S3C72K8, both in function and in pin configuration.
product overview S3C72K8/p72k8 1- 2 features memory ? 8 k 8 -bit ram ? 1,024 4 -bit rom 27 i/o pins ? input only: 4 pins ? i/o: 15 pins ? output: maximum 8 pins for 1-bit level output (sharing with segment driver outputs) comparator ? two channel mode: internal reference (4-bit resolution) ? one channel mode: external reference lcd controller/driver ? 40 segments and 8 common terminals ? 3, 4 and 8 common selectable ? internal resistor circuit for lcd bias ? all dot can be switched on/off 8-bit basic timer ? 4 interval timer functions ? watchdog timer 8-bit timer/counter ? programmable 8-bit timer ? external event counter ? arbitrary clock frequency output ? external clock signal divider ? serial i/o interface clock generator 8-bit serial i/o interface ? 8-bit transmit/receive mode ? 8-bit receive only mode ? lsb-first or msb-first transmission selectable ? internal or external clock source bit sequential carrier ? support 16-bit serial data transfer in arbitrary format watch timer ? timer interval generation: 0.5 s, 3.9 ms at 32,768 hz ? four frequency outputs to buz pin ? clock source generation for lcd interrupts ? three internal vectored interrupts : intb, intt0, ints ? four external vectored interrupts : int0, int1, int4, intk ? two quasi-interrupts : int2, intw memory-mapped i/o structure ? data memory bank 15 two power-down modes ? idle mode (only cpu clock stops) ? stop mode (main system oscillation stops) ? subsystem clock stop mode oscillation sources ? crystal, ceramic, or external rc for system clock ? main system clock frequency: 0.4 mhz ?6 mhz ? subsystem clock frequency: 32 , 768 khz ? cpu clock divider circuit (by 4, 8, or 64) instruction execution times ? 0.67 us at 6 mhz (minimum) ? 0.95 m s at 4.19 mhz (minimum) ? 122 m s at 32, 768 khz (minimum) operating temperature ? ? 40 c to 85 c operating voltage range ? 2.0 v to 5.5 v package type ? 80 -pin qfp
S3C72K8/p72k8 product overview 1- 3 block diagram program status word arithmetic and logic unit instruction decoder internal interrupts reset interrupt control block stack pointer clock 8 kbyte program memory 1024 x 4-bit data memory x in xt in program counter flags p0.0/sck/k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 x out xt out watchdog timer input port 1 comparator i/o port 0 watch timer basic timer sio p1.0/int0/cin0 p1.1/int1/cin1 p1.2/int2 p1.3/int4 lcd driver/ controller i/o port 4 8-bit timer/ counter i/o port 2 i/o port 3 v lc1 -v lc5 com0-com7 seg0-seg31 p5.0/seg32- p5.7/seg39 p2.0-p2.3 p3.0 p3.1 p3.2/lcdsy p3.3/cldck p4.0/clo p4.1/tcl0 p4.2/tclo0 figure 1 -1 . S3C72K8 simplified block diagram
product overview S3C72K8/p72k8 1- 4 pin assignments S3C72K8 (80-qfp-1420c) p5.6/seg38 p5.7/seg39 v lc1 v lc2 v lc3 v lc4 v lc5 p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 v dd v ss x out x in test xt in xt out reset p1.0/int0/cin0 p1.1/int1/cin1 p1.2/int2 p1.3/int4 p2.0 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 com5 com4 com3 com2 com1 com0 tclo0/p4.2 tcl0/p4.1 clo/p4.0 lcdck/p3.3 lcdsy/p3.2 p3.1 p3.0 p2.3 p2.2 p2.1 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32/p5.0 seg33/p5.1 seg34/p5.2 seg35/p5.3 seg36/p5.4 seg37/p5.5 figure 1 -2 . S3C72K8 80- qfp pin assignment
S3C72K8/p72k8 product overview 1- 5 pin descriptions table 1 - 1. S3C72K8 pin descriptions pin name pin type description circuit type pin number share pin p0.0 p0.1 p0.2 p0.3 i/o 4-bit i/o port. 1-bit or 4-bit read/write and test is pos sible. individual pins are software configurable as input or output. individual pins are software configurable as open- drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. e?2 8 9 10 11 k0/ sck k1/so k2/si k3/buz p1.0 p1.1 p1.2 p1.3 i 4-bit input port. 1-bit or 4-bit read and test are possible. the 1-bit unit pull-up resistors are assigned to input pins by software. an interrupt is generated by digital input at p1.0, p1.1. f?4 f?4 a?3 a?3 20 21 22 23 int0/cin0 int1/cin1 int2 int4 p2.0?p2.3 i/o same as port 0 except that 8-bit read/write and test is possible. e?2 24?27 ? p3.0 p3.1 p3.2 p3.3 28 29 30 31 ? ? lcdsy lcdck p4.0 p4.1 p4.2 i/o same as port 0 except that port 4 is 3-bit i/o port. e?2 32 33 34 clo tcl0 tclo0 p5.0?p5.7 o output port for 1-bit data h?11 75? 80,1,2 seg32? seg39 sck i/o serial i/o interface clock signal e?2 8 p0.0/k0 so i/o serial data output e?2 9 p0.1/k1 si i/o serial data input e?2 10 p0.2/k2 buz i/o 2 khz, 4 khz, 8 khz or 16 khz frequency output at the watch timer clock frequency of 32.768 khz. e?2 11 p0.3/k3 k0?k3 i/o external interrupt. the triggering edge is selectable. e?2 8?11 p0.0?p0.3 int0 int1 i external interrupts. the triggering edge for int0 and int1 is selectable. f?4 20 21 p1.0/cin0 p1.1/cin1 int2 i quasi-interrupt with detection of rising or falling edges a?3 22 p1.2 int4 i external interrupts with detection of rising and falling edges a?3 23 p1.3
product overview S3C72K8/p72k8 1- 6 table 1 - 1. S3C72K8 pin descriptions (continued) pin name pin type description circuit type pin number share pin cin0 cin1 i 2-channel comparator input. cin0: comparator input or external reference input cin1: compara tor input only. f?4 20 21 p1.0/int0 p1.1/int1 lcdsy i/o lcd synchronization clock output for display expansion e?2 30 p3.2 lcdck i/o lcd clock output for display expansion e?2 31 p3.3 clo i/o clock output e?2 32 p4.0 tcl0 i/o external clock input for timer/counter 0 e?2 33 p4.1 tclo0 i/o timer/counter 0 clock output e?2 34 p4.2 seg32? seg39 o lcd segment signal output h?11 75? 80,1,2 p5.0?p5.7 seg0? seg31 o lcd segment signal output h?6 43?74 ? com0? com7 o lcd common signal output h?6 35?42 ? v lc1 ?v lc5 ? lcd power supply. voltage dividing resistors are assignable by mask option. ? 3?7 ? x in , x out ? crystal, ceramic or rc oscillator pins for system clock. ? 15, 14 ? xt in , xt out ? crystal oscillator pins for subsystem clock. ? 17, 18 ? v dd ? main power supply ? 12 ? v ss ? ground ? 13 ? reset i chip reset signal input b 19 ? test i chip test signal input (must be connected to v ss ) ? 16 ? note: pull-up resistors for all i/o ports are automatically disabled if they are configured to output mode
S3C72K8/p72k8 product overview 1- 7 pin circuit diagrams p-channel n-channel in v dd figure 1 -3 . pin circuit type a in v dd pull-up resistor enable p-channel pull-up resistor schmitt trigger figure 1 -4 . pin circuit type a-3 schmitt trigger in v dd pull-up resistor figure 1 -5 . pin circuit type b p-channel n-channel v dd out output disable data figure 1 -6 . pin circuit type 7
product overview S3C72K8/p72k8 1- 8 schmitt trigger n-ch v dd resistor enable v dd i/o pne pull-up resistor p-ch output disable data figure 1-7. pin circuit type e-2 i/o schmitt trigger resistor enable v dd pull-up resistor + - ext-ref (p1.0 only) analog in digital in comparator int-ref digital or analog selectable by software (p1mod) figure 1-8. pin circuit type f-4
S3C72K8/p72k8 product overview 1- 9 out v lc3 seg/com data v lc2 output disable v dd v lc1 v lc4 v lc5 figure 1-9. pin circuit type h-5
product overview S3C72K8/p72k8 1- 10 out seg/com v lc1 v lc2 v dd v lc4 v lc3 v lc5 figure 1-10. pin circuit type h-6 p-ch n-ch v dd out output disable 1 data circuit type h-5 n-ch seg output disable 2 figure 1-11. pin circuit type h-11
S3C72K8/p72k8 address spaces 2 - 1 2 address spaces program memory (rom) overview rom maps for S3C72K8 devices are mask programmable at the factory . in its standard c onfiguration, the device's 8,192 8-bit program memory has three areas that are directly addressable by the program counter (pc): ? 16 -byte area for vector addresses ? 96-byte instruction reference area ? 16 -byte general-purpose area ? 8,064 -byte general-purpose area general-purpose program memory two program memory areas are allocated for general-purpose use: one area is 16 bytes in size and the other is 8,064 bytes . vector addresses a 16 -byte vector address area is used to store the vector addresses required to execute system resets and interrupts. start addresses for interrupt service routines are stored in this area, along with the values of the enable memory bank (emb) and enable register bank (erb) flags that are used to set th eir initial value for the corre sponding service routines. the 1 6 -byte area can be used alternately as general-purpose rom. ref instructions locations 0020h?007fh are used as a reference area (look-up table) for 1-byte ref instructions. the ref instruction reduces the byte size of instruction operands. ref can reference one 2 -byte instruction, two 1-byte instructions, and 3 -byte instructions which are stored in the look-up table. unused look-up table addresses can be used as general-purpose rom. table 2- 1. program memory address ranges rom area function address ranges area size (in bytes) vector address area 0000h ?000fh 16 general-purpose program memory 0010h?001fh 16 ref instruction look-up table area 0020h?007fh 96 general-purpose program memory 0080h?1fffh 8,064
address spaces s3c72 k8/p72k8 2 - 2 general-purpose memory areas the 16-byte area at rom locations 000c h?001fh and the 8,064 -byte area at rom locations 0080h? 1 fffh are used as general-purpose program memory. unused locations in the vector address area and ref instruction look-up table areas can be used as general-purpose program memory. however, care must be taken not to overwrite live data when writing programs that use special-purpose areas of the rom. vector address area the 1 6 -byte vector address area of the rom is used to store the vector addresses for executing system resets and interrupts. the starting addresses of interrupt service routines are stored in this area, along with the enable memory bank (emb) and enable register bank (erb) flag values that are needed to initialize the service routines. 16 -byte vector addresses are organized as follows: emb erb 0 pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 to set up the vector address area for specific programs, use the instruction ventn. the programming tips on the next page explain how to do this. vector address area (16 bytes) general- purpose area (16 bytes) instruction reference area (96 bytes) general-purpose area (8,064 byte) 1fffh 007fh 0080h 001fh 0020h 000fh 0010h 0000h figure 2- 1. rom address structure 0000h reset intb/int4 int0 int1 ints intt0 intk 7 6 5 4 3 2 1 0 0002h 0004h 0006h 0008h 000ah 000ch figure 2-2 . vector address structure
S3C72K8/p72k8 address spaces 2 - 3 + + programming tip ? defining vectored interrupts the following examples show you several ways you can define the vectored interrupt and instruction referen ce areas in program memory: 1. when all vector interrupts are used: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent2 0,0,int0 ; emb ? 0, erb ? 0; jump to int0 address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address vent4 0,0,ints ; emb ? 0, erb ? 0; jump to int s address vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to int t0 address vent6 0,0,intk ; emb ? 0, erb ? 0; jump to int k address 2. when a specific vectored interrupt such as int0, and intt0 is not used, the unused vector interrupt locations must be skipped with the assembly instruction org so that jumps will address the correct locations: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address org 0006h ; int0 interrupt not used vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int1 address vent4 0,0,ints ; emb ? 0, erb ? 0; jump to int s address ; org 000ch ; intt0 interrupt not used ; vent6 0,0,intk ; emb ? 0, erb ? 0; jump to int k address 3. if an int0 interrupt is not used and if its corresponding vector interrupt area is not fully utilized, or if it is not written by a org instruction as in example 2, a cpu malfunction will occur: org 0000h ; vent0 1,0, reset ; emb ? 1, erb ? 0; jump to reset address vent1 0,0,intb ; emb ? 0, erb ? 0; jump to intb address vent3 0,0,int1 ; emb ? 0, erb ? 0; jump to int0 address vent4 0,0,ints ; e mb ? 0, erb ? 0; jump to int1 address vent5 0,0,intt0 ; emb ? 0, erb ? 0; jump to int s address vent6 0,0,intk ; emb ? 0, erb ? 0; jump to int t0 address ; org 0010h ; general-purpose rom area in this example, when an int s interrupt is generated, the corresponding vector area is not vent 4 int s , but vent5 intt0. this causes an int s interrupt to jump incorrectly to the intt0 address and causes a cpu malfunction to occur.
address spaces s3c72 k8/p72k8 2 - 4 instruction reference area using 1-byte ref instructions, you can easily reference instructions with larger b yte sizes that are stored in ad dresses 0020h?007fh of program memory. this 96-byte area is called the ref instruction reference area, or look-up table. locations in the ref look-up table may contain two one-byte instruct ions, a single two-byte instruc tion, or three-byte instruction such as a jp (jump) or call. the starting address of the instruction you are referencing must always be an even number. to reference a jp or call instruction, it must be written to the reference area in a two-byte format: for jp, this format is tjp; for call, it is tcall. in summary, there are three ways to the ref instruction: by using ref instructions to execute instructions larger than one byte, you can improve program execution time considerably by reducing the number of program steps. in summary, there are three ways you can use the ref instruction: ? using the 1-byte ref instruction to execute one 2-byte or two 1-byte instructions, ? branching to any location by referencing a branch instruction stored in the look-up table, ? calling subroutines at any location by referencing a call instruction stored in the look-up table. + + programming tip ? using the ref look-up table here is one example of how to use the ref instruction look-up table: org 0020h ; jmain tjp main ; 0, main keyck btsf keyfg ; 1, keyfg check watch tcall clock ; 2, call clock inchl ld @hl,a ; 3, (hl) ? a incs hl ? ? ? abc ld ea,#00h ; ea ? #00h org 0080 h ; main nop nop ? ? ? ref keyck ; btsf keyfg (1-byte instruction) ref jmain ; keyfg = 1, jump to main (1-byte instruction) ref watch ; keyfg = 0, call clock (1-byte instruction) ref inchl ; ld @hl,a ; incs hl ref abc ; ld ea,#00h (1-byte instruction) ? ? ?
S3C72K8/p72k8 address spaces 2 - 5 data memory (ram) overview in its standard configuration, the 1,024 x 4 -b it data memory has three areas: ? 32 4-bit working register area in bank 0 ? 224 4 -bit general-purpose area in bank 0 which is also used as the stack area ? 176 4 -bit general-purpose area in bank 1 ? 80 4 -bit area for lcd data in bank 1 ? 256 4 -bit general-purpose area in bank 2 ? 256 4 -bit general-purpose area in bank 3 ? 128 4-bit area in bank 15 for memory-mapped i/o addresses to make it easier to reference, the data memory area has five memory banks ? bank 0, bank 1 , bank 2, babk 3, and bank 15. the select memory bank instruction (smb) is used to select the bank you want to select as working data memory. data stored in ram locations are 1-, 4-, and 8-bit addressable. initialization values for the data memory area are not defined by hardware and must therefore be initialized by program software following power reset . however, when reset signal is generated in power-down mode, the data memory contents are held. general-purpose registers and stack area (224 x 4 bits) working registers (32 x 4 bits) general-purpose registers (176 x 4 bits) memory-mapped i/o address registers (128 x 4 bits) bank 0 bank 15 000h 01fh 020h 0ffh 100h 1ffh 200h 3ffh fffh f80h bank 1 lcd data registers (80 x 4 bits) 1afh 1b0h general-purpose registers (256 x 4 bits) general-purpose registers (256 x 4 bits) bank 3 bank 2 2ffh 300h figure 2-3. data memory (ram) map
address spaces s3c72 k8/p72k8 2 - 6 memory banks 0, 1, and 15 bank 0 (000h?0ffh) the lowest 32 nibbles of bank 0 (000h?01fh) are used as working registers; the next 224 nibbles (020h?0ffh) can be used both as stack area and as general-purpose data memory. use the stack area for implementing subroutine calls and returns, and for interrupt processing. bank 1 (1 e 0h?1ffh) the lowest 176 nibbles of bank 1 (100h?1afh) are for general-purpose use; use the ramaining of 80 nibbles (1b0h?1ffh) as display registers or as general purpose memory. bank 2 (200h?2ffh) 256 nibbles of bank 2 (200h?2ffh) are for general-purpose used bank 3 (300h?3ffh) 256 nibbles of bank 3 (300h?3ffh) are for general-purpose used bank 15 (f80h?fffh) the microcontroller uses bank 15 for memory-mapped peripheral i/o. fixed ram locations for each peripheral hardware address are mapped into this area. data memory addressing modes the enable memory bank (emb) flag controls the addressing mode for data memory banks 0, 1 , 2, 3 or 15. when the emb flag is logic zero, the addressable area is restricted to specific locations, depending on whether direct or indirect addressing is used. with direct addressing, you can access locations 000h?07fh of bank 0 and bank 15. with indirect addressing, only bank 0 (000h?0ffh) can be accessed. when the emb flag is set to logic one, all three data memory banks can be accessed according to the current smb value. for 8-bit addressing, two 4-bit registers are addressed as a register pair. also, when using 8-bit instructions to address ram locations, remember to use the even-numbered register address as the instruction operand. working registers the ram working register area in data memory bank 0 is further divided into four register banks (bank 0, 1, 2, and 3). each register bank has eight 4-bit registers and paired 4-bit registers are 8-bit addressable. register a is used as a 4-bit accumulator and register pair ea as an 8-bit extended accumulator. the carry flag bit can also be used as a 1-bit accumulator. register pairs wx, wl, and hl are used as address pointers for indirect addressing. to limit the possibility of data corruption due to incorrect register addressing, it is advisable to use register bank 0 for the main program and banks 1, 2, and 3 for interrupt service routines. lcd data register area bit values for lcd segment data are stored in data memory bank 1. register locations in this area that are not used to store lcd data can be assigned to general-purpose use.
S3C72K8/p72k8 address spaces 2 - 7 table 2- 2. data memory organization and addressing addresses register areas bank emb value smb value 000h ? 01fh working registers 0 0, 1 0 020h ? 0ffh stack and general-purpose registers 100h?1afh general-purpose registers 1 1 1 1b0h?1ffh lcd data registers 200h?2ffh general-purpose registers 2 1 2 300h?3ffh general-purpose registers 3 1 3 f80h?fffh i/o- mapped hardware registers 15 0, 1 15 + + programming tip ? clearing data memory banks 0 and 1 clear banks 0 and 1 of the data memory area: ramclr smb 1 ; ram ( 100h?1ffh ) clear ld hl, #00h ld a, #0h rmcl1 ld @hl, a incs hl jr rmcl1 ; smb 0 ; ram ( 020 h ? 0ffh) clear ld hl, # 20 h rmcl0 ld @hl, a incs hl jr rmcl0
address spaces s3c72 k8/p72k8 2 - 8 working registers working registers, mapped to ram address 000h ? 01fh in data memory bank 0, are used to temporarily store intermediate results during program execution, as well as pointer values used for indirect addressing. unused registers may be used as general-purpose memory. working register data can be manipulated as 1-bit units, 4-bit units or, using paired registers, as 8-bit units. a e l h x w z y a ...y a ...y a ...y 000h 001h 002h 003h 004h 005h 006h 007h 008h 00fh 010h 017h 018h 01fh register bank 1 register bank 2 register bank 3 working register bank 0 data memory bank 0 figure 2-4 . working register map
S3C72K8/p72k8 address spaces 2 - 9 working register banks for addressing purposes, the working register area is divided into four register banks ? bank 0, bank 1, bank 2, and bank 3. any one of these banks can be selected as the working register bank by the register bank selection instruction (srb n) and by setting the status of the register bank enable flag (erb). generally, working register bank 0 is used for the main program, and banks 1, 2, and 3 for interrupt service rou tines. following this convention helps to prevent possible data corruption duri ng program execution due to con tention in register bank addressing. table 2- 3. working register organization and addressing erb srb settings selected register bank setting 3 2 1 0 0 0 0 ? ? always set to bank 0 0 0 bank 0 1 0 0 0 1 bank 1 1 0 bank 2 1 1 bank 3 note: 'x' means don't care. paired working registers each of the register banks is subdivided into eight 4-bit registers. these registers, named y, z, w, x, h, l, e , and a, can either be manipulated individually using 4-bit instructions, or together as register pai rs for 8-bit data manipulation. the names of the 8-bit register pairs in each register bank are ea, hl, wx, yz , and wl. registers a, l, x , and z always become the lower nibble when registers are addressed as 8-bit pairs. this makes a total of eight 4-bit registers or four 8-bit double registers in each of the four working register banks. (msb) (lsb) (msb) (lsb) y w h e z x l a figure 2-5. register pair configuration
address spaces s3c72 k8/p72k8 2 - 10 special-purpose working registers register a is used as a 4-bit accumulator and double register ea as an 8-bit accumulator. the carry flag can also be used as a 1-bit accumulator. 8-bit double registers wx, wl , and hl are used as data pointers for indirect addressing. when the hl register serves as a data pointer, the instructions ldi, ldd, xchi, and xchd can make very efficient use of working registers as program loop counters by letting you transfer a value to the l register and increment or decrement it using a single instruction. c a ea 1-bit accumulator 4-bit accumulator 8-bit accumulator figure 2-6 . 1-bit, 4-bit, and 8-bit accumulator recommendation for multiple interrupt processing if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are executed in the same register bank. when the routines have executed successfully, you can restore the register contents from the stack to working memory using the pop instruction.
S3C72K8/p72k8 address spaces 2 - 11 + + programming tip ? selecting the working register area the following examples show the correct programming method for selecting working register area: 1. when erb = "0": vent2 1,0,int0 ; emb ? 1, erb ? 0, jump to int0 address ; int0 push sb ; push current smb, srb srb 2 ; instruction does not execute because erb = "0" push hl ; push hl register contents to stack push wx ; push wx register contents to stack push yz ; push yz register contents to stack push ea ; push ea register contents to stack smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop ea ; pop ea re gister contents from stack pop yz ; pop yz register contents from stack pop wx ; pop wx register contents from stack pop hl ; pop hl register contents from stack pop sb ; pop current smb, srb iret the pop instructions execute alternately with the push instructions. if an smb n instruction is used in an interrupt service routine, a push and pop sb instruction must be used to store and restore the current smb and srb values, as shown in example 2 below. 2. when erb = "1": vent2 1,1,int0 ; emb ? 1, erb ? 1, jump to int0 address ; int0 push sb ; store current smb, srb srb 2 ; select register bank 2 because of erb = "1" smb 0 ld ea,#00h ld 80h,ea ld hl,#40h incs hl ld wx,ea ld yz,ea pop sb ; restore smb, srb iret
address spaces s3c72 k8/p72k8 2 - 12 stack operations stack pointer (sp) the stack pointer (sp) is an 8-bit register that stores the address used to access the stack, an area of data memory set aside for temporary storage of data and addresses. the sp can be read or w ritten by 8 -bit control instruc tions. when addressing the sp, bit 0 must always remain cleared to logic zero. f80h sp3 sp2 sp1 "0" f81h sp7 sp6 sp5 sp4 there are two basic stack operations: writing to the top of the stack (push), and reading from the top of the stack (pop). a push decrements the sp and a pop increments it so that the sp always points to the top address of the last data to be written to the stack. the program counter contents and program status word (psw) are stored in the stack area prior to the execution of a call or a push instruction, or during interrupt service routines. stack operation is a lifo (last in-first out) type. the stack area is located in general-purpose data memory bank 0. during an interrupt or a subroutine, the pc value and the psw are saved to the stack area. when the routine has completed, the stack pointer is referenced to restore the pc and psw, and the next instruction is executed. the sp can address stack registers in bank 0 (addresses 000h ? 0ffh) regardless of the current value of the en able memory bank (emb) flag and the select memory bank (smb) flag. although general-purpose register areas can be used for stack operations, be careful to avoid data loss due to simultaneous use of the same register(s). since the reset value of the stack pointer is not defined in firmware, we recommend that you initialize the stack pointer by program code to location 00h. this sets the first register of the stack area to 0ffh. note a subroutine call occupies six nibbles in the stack; an interrupt requires six. when subroutine nesting or interrupt routines are used continuously, the stack area should be set in accordance with the maximum number of subroutine levels. to do this, estimate the number of nibbles that will be used for the subroutines or interrupts and set the stack area correspondingly. + + p rogramming tip ? initializing the stack pointer to initialize the stack pointer (sp): 1. when emb = "1": smb 1 5 ; select memory bank 15 ld ea,#00h ; bit 0 of sp is always cleared to "0" ld sp,ea ; stack area initial address (0ffh) ? (sp) ? 1 2. when emb = "0": ld ea,#00h ld sp,ea ; memory addressing area (00h ? 7fh, f80h ? fffh)
S3C72K8/p72k8 address spaces 2 - 13 push operations three kinds of push operations reference the stack pointer (sp) to write data from the source register to the stack: push instructions, call instructions, and interrupts. in each case, the sp is decreased by a number determined by the type of push operation and then points to the next available stack location. push instructions a push instruction references the sp to write two 4-bit data nibbles to the stack. two 4-bit stack addresses are referenced by the stack pointer: one for the upper register value and another for the lower register. after the push has executed, the sp is decreased by two and points to the next available stack location. call instructions when a subroutine call is issued, the call instruction references the sp to write the pc's contents to six 4 -bit stack locations. current values for the enable memory bank (emb) flag and the enable register bank (erb) flag are also pushed to the stack. since six 4-bit stack locations are used per call, you may nest subroutine calls up to the number of levels permitted in the stack. interrupt routines an interrupt routine references the sp to push the contents of the pc and the program status word (psw) to the stack. six 4-bit stack locations are used to store this data. after the interrupt has executed, the sp is decreased by six and points to the next available stack location. during an interrupt sequence, subroutines may be nested up to the number of levels which are permitted in the stack area. lower register upper register sp -2 sp -1 sp push (after push, sp sp-2) sp -1 sp call (after call , sp sp-6) pc11-pc8 0 0 pc3-pc0 pc7-pc4 0 0 emb erb 0 0 0 0 sp -2 sp -3 sp -4 sp -5 sp -6 sp -1 sp interrupt (when int is acknowledged, sp sp-6) pc11-pc8 0 pc3-pc0 pc7-pc4 is1 is0 emb erb c sp -2 sp -3 sp -4 sp -5 sp -6 psw sc2 sc1 sc0 0 0 0 psw 0 0 figure 2-7 . push-type stack operations
address spaces s3c72 k8/p72k8 2 - 14 pop operations for each push operation there is a corresponding pop operation to write data from the stack back to the source register or registers: for the push instruction it is the pop instruction; for call, the instruction ret or sret; for interrupts, the instruction iret. when a pop operation occurs, the sp is incremented by a number determined by the type of operation and points to the next free stack location. pop instructions a pop instruction references the sp to write data stored in two 4-bit stack locations back to the register pairs and sb register. the value of the lower 4-bit register is popped first, followed by the value of the upper 4-bit register. after the pop has executed, the sp is incremented by two and points to the next free stack location. ret and sret instructions the end of a subroutine call is signaled by the return instruction, ret or sret. the ret or sret uses the sp to reference the six 4-bit stack locations used for the call and to write this data back to the pc, the emb, and the erb. after the ret or sret has executed, the sp is incremented by six and points to the next free stack location. iret instructions the end of an interrupt sequence is signaled by the instruction iret. iret references the sp to locate the six 4- bit stack addresses used for the interrupt and to write this data back to the pc and the psw. after the iret has executed, the sp is incremented by six and points to the next free stack location. sp pc11-pc8 0 pc3-pc0 pc7-pc4 0 0 emb erb 0 0 0 0 pc11-pc8 0 0 pc3-pc0 pc7-pc4 is1 is0 emb erb c psw sc2 sc1 sc0 iret (sp sp+6) ret or sret (sp sp+6) pop (sp sp+2) sp +1 sp +2 lower register upper register sp +5 sp+6 sp+4 sp +3 sp +2 sp +1 sp sp +5 sp+6 sp+4 sp +3 sp +2 sp +1 sp 0 0 0 psw 0 0 figure 2-8 . pop-type stack operations
S3C72K8/p72k8 address spaces 2 - 15 bit sequential carrier (bsc) the bit sequential carrier (bsc) is a 16-bit general register that can be manipulated using 1-, 4-, and 8-bit ram control instructions. reset clears all bsc bit values to logic zero. using the bsc, you can specify sequential addresses and bit locations using 1-bit indirect addressing ( memb.@l). (bit addressing is independent of the current emb value.) in this way, programs can process 16-bit data by moving the bit location sequentially and then incrementing or decreasing the value of the l register. bsc data can also be manipulated using direct addressing. for 8-bit manipulations, the 4-bit register names bsc0 and bsc2 must be specified and the upper and lower 8 bits manipulated separately. if the values of the l register are 0h at bsc0.@l, the address and bit location assignment is fc0h.0. if the l register content is fh at bsc0.@l, the address and bit location assignment is fc3h.3. table 2- 4. bsc register organization name address bit 3 bit 2 bit 1 bit 0 bsc0 fc0h bsc0.3 bsc0.2 bsc0.1 bsc0.0 bsc1 fc1h bsc1.3 bsc1.2 bsc1.1 bsc1.0 bsc2 fc2h bsc2.3 bsc2.2 bsc2.1 bsc2.0 bsc3 fc3h bsc3.3 bsc3.2 bsc3.1 bsc3.0 + + programming tip ? using the bsc register to output 16-bit data to use the bit sequential carrier (bsc) register to output 16-bit data (5937h) to the p3.0 pin: bits emb smb 15 ld ea,#37h ; ld bsc0,ea ; bsc0 ? a, bsc1 ? e ld ea,#59h ; ld bsc2,ea ; bsc2 ? a, bsc3 ? e smb 0 ld l,#0h ; agn ldb c,bsc0.@l ; ldb p3.0,c ; p3.0 ? c incs l jr agn ret
address spaces s3c72 k8/p72k8 2 - 16 program counter (pc) a 12 -bit program counter (pc) stores addresses for instruction f etches during program execution. whenever a reset operation o r an interrupt occurs, bits pc11 through pc0 are set to the vector address. usually, the pc is incremented by the number of bytes of the instruction being fetched. one exception is the 1- byte ref instruction which is used to reference instructions stored in the rom. program status word (psw) the program status word (psw) is an 8-bit word that defines system status and program execution status and which permits an interrupted process to resume operation after an inter rupt request has been serviced. psw values are mapped as follows: (msb) (lsb) fb0h is1 is0 emb erb fb1h c sc2 sc1 sc0 the psw can be manipulated by 1-bit or 4-bit read/write and by 8-bit read ins tructions, depending on the spe cific bit or bits being addressed. the psw can be addressed during program execution regardless of the current value of the enable memory bank (emb) flag. part or all of the psw is saved to stack prior to execution of a subroutine call or h ardware interrupt. after the in terrupt has been processed, the psw values are popped from the stack back to the psw address. when a reset is generated, the emb and erb values are set according to the reset vector address, and the carry flag is left undefined (or the current value is retained). psw bits is0, is1, sc0, sc1, and sc2 are all cleared to logical zero. table 2- 5. program status word bit descriptions psw bit identifier description bit addressing read/write is1, is0 interrupt status flags 1, 4 r/w emb enable memory bank flag 1 r/w erb enable register bank flag 1 r/w c carry flag 1 r/w sc2, sc1, sc0 program skip flags 8 r
S3C72K8/p72k8 address spaces 2 - 17 interrupt status flags (is0, is1) psw bits is0 and is1 contain the current interrupt execution status values. you can manipulate is0 and is1 flags directly using 1-bit ram control instructions by manipulating interrupt status flags in conjunction with the interrupt priority register (ipr), you can process multiple interrupts by anticipating the next interrupt in an execution sequence. the interrupt priority control circuit determines the is0 and is1 settings in order to control multiple interrupt processing. when both interrupt status flags are set to "0", all interrupts are allowed. the priority with which interrupts are processed is then determined by the ipr. when an interrupt occurs, is0 and is1 are pushed to the stack as part of the psw and are automatically incremented to the next higher priority level. then, when the interrupt service routine ends with an iret instruction, is0 and is1 values are restored to the psw. table 2- 6 shows the effects of is0 and is1 flag settings. table 2- 6. interrupt status flag bit settings is1 value is0 value status of currently executing process effect of is0 and is1 settings on interrupt request control 0 0 0 all interrupt requests are serviced 0 1 1 only high-priority interrupt(s) as determined in the interrupt priority register (ipr) are serviced 1 0 2 no more interrupt requests are serviced 1 1 ? not applicable; these bit settings are undefined since interrupt status flags can be addressed by write instructions, programs can exert direct control over inter rupt processing status. before interrupt status flags can be addressed, however, you must first execute a di in struction to inhibit additional interrupt routines. when the bit manipulation has been completed, execute an ei instruction to re- enable interrupt processing. + + programming tip ? setting isx flags for interrupt processing the following instruction sequence shows how to use the is0 and is1 flags to control interrupt processing: intb di ; disable interrupt bitr is1 ; is1 ? 0 bits is0 ; allow interrupts according to ipr priority level ei ; enable interrupt . . . iret
address spaces s3c72 k8/p72k8 2 - 18 emb flag (emb) the emb flag is used to allocate specific address locations in the ram by modifying the upper 4 bits of 12-bit data memory addresses. in this way, it controls the addressing mode for data memory banks 0, 1 , or 15. when the emb flag is "0", the data memory address space is restricted to bank 15 and addresses 000h?07fh of memory bank 0, regardless of the smb register contents. when the emb flag is set to "1", the general-purpose areas of bank 0, 1 , and 15 can be accessed by using the appropriate smb value. + + programming tip ? using the emb flag to select memory banks emb flag settings for memory bank selection: 1. when emb = "0": smb 1 ; non-essential instruction since emb = "0" ld a,#9h ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h ,a ; (034h) ? a, bank 0 is selected smb 0 ; non-essential instruction since emb = "0" ld 90h,a ; (f90h) ? a, bank 15 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; non-essential instruction, since emb = "0" ld 20h,a ; (020h) ? a, bank 0 is selected ld 90h,a ; (f90h) ? a, bank 15 is selected 2. when emb = "1": smb 1 ; select memory bank 1 ld a,#9h ld 90h ,a ; (1 90 h) ? a, bank 1 is selected ld 34h ,a ; ( 1340 h) ? a, bank 1 is selected smb 0 ; select memory bank 0 ld 90 h,a ; (090h) ? a, bank 0 is selected ld 34h,a ; (034h) ? a, bank 0 is selected smb 15 ; select memory bank 15 ld 20h,a ; program error, but assembler does not detect it ld 90h,a ; (f90h) ? a, bank 15 is selected
S3C72K8/p72k8 address spaces 2 - 19 erb flag (erb) the 1-bit register bank enable flag (erb) determines the range of addressable working register area. when the erb flag is "1", the working register area from register banks 0 to 3 is selected according to the register bank selection register (srb). when the erb flag is "0", register bank 0 is the selected working register area, regardless of the current value of the register bank selection register (srb). when an internal reset is generated, bit 6 of program memory address 0000h is written to the erb flag. this automatically initializes the flag. when a vectored interrupt is generated, bit 6 of the respective address table in program memory is written to the erb flag, setting the correct flag status before the interrupt service routine is executed. during the interrupt routine, the erb value is automatically pushed to the stack area along with the other psw bits. afterwards, it is popped back to the fb0h.0 bit location. the initial erb flag settings for each vectored interrupt are defined using ventn instructions. + + programming tip ? using the erb flag to select register banks erb flag settings for register bank selection: 1. when erb = "0": srb 1 ; register bank 0 is selected (since erb = "0", the ; srb is configured to bank 0) ld ea,#34h ; bank 0 ea ? #34h ld hl,ea ; bank 0 hl ? ea srb 2 ; register bank 0 is selected ld yz,ea ; bank 0 yz ? ea srb 3 ; register bank 0 is selected ld wx,ea ; bank 0 wx ? ea 2. when erb = "1": srb 1 ; register bank 1 is selected ld ea,#34h ; bank 1 ea ? #34h ld hl,ea ; bank 1 hl ? bank 1 ea srb 2 ; register bank 2 is selected ld yz,ea ; bank 2 yz ? b ank 2 ea srb 3 ; register bank 3 is selected ld wx,ea ; bank 3 wx ? bank 3 ea
address spaces s3c72 k8/p72k8 2 - 20 skip condition flags (sc2, sc1, sc0) the skip condition flags sc2, sc1, and sc0 in the psw indicate the current program skip conditions and are set and reset automatically during program execution. skip condition flags can only be addressed by 8-bit read instructions. direct manipulation of the sc2, sc1, and sc0 bits is not allowed. carry flag (c) the carry flag is used to save the result of an overflow or borrow when executing arithmetic instructions involving a carry (adc, sbc). the carry flag can also be used as a 1-bit accumulator for performing boolean operations involving bit-addressed data memory. if an overflow or borrow condition occurs when executing arithmetic instructions with carry (adc, sbc), the carry flag is set to "1". otherwise, its value is "0". when a reset occurs, the current value of the carry flag is retained during power-down mode, but when normal operating mode resumes, its value is undefined. the carry flag can be directly manipulated by predefined set of 1-bit read/write instructions, independent of other bits in the psw. only the adc and sbc instructions, and the instructions listed in table 2- 7, affect the carry flag. table 2- 7. valid carry flag manipulation instructions operation type instructions carry flag manipulation direct manipulation scf set carry flag to "1" rcf clear carry flag to "0" (reset carry flag) ccf invert carry flag value (complement carry flag) btst c test carry and skip if c = "1" bit transfer ldb (operand) (1) ,c load carry flag value to the specified bit ldb c,(operand) (1) load contents of the specified bit to carry flag boolean manipulation band c,(operand) (1) and the specified bit with contents of carry flag and save the result to the carry flag bor c,(operand) (1) or the specified bit with contents of carry flag and save the result to the carry flag bxor c,(operand) (1) xor the specified bit with contents of carry flag and save the result to the carry flag interrupt routine intn (2) save carry flag to stack with other psw bits return from interrupt iret restore carry flag from stack with other psw bits notes : 1. the operand has three bit addressing formats: mema.a, memb.@l, and @h + da.b. 2. ' intn' refers to the specific interrupt being executed and is not an instruction.
S3C72K8/p72k8 address spaces 2 - 21 + + programming tip ? using the carry flag as a 1-bit accumulator 1. set the carry flag to logic one: scf ; c ? 1 ld ea,#0c3h ; ea ? #0c3h ld hl,#0aah ; hl ? #0aah adc ea,hl ; ea ? #0c3h + #0aah + #1h, c ? 1 2. logical-and bit 3 of address 3fh with p3.3 and output the result to p 5 .0: ld h,#3h ; set the upper four bits of the address to the h register ; value ldb c,@h+0fh.3 ; c ? bit 3 of 3fh band c,p3.3 ; c ? c and p3.3 ldb p 4 .0,c ; output result from carry flag to p 4 .0
S3C72K8/p72k8 addressing modes 3 - 1 3 addressing modes overview the enable memory bank flag, emb, controls the two addressing modes for data memory. when the emb flag is set to logic one, you can address the entire ram area; when the emb flag is cleared to logic zero, the addressable area in the ram is restricted to specific locations. the emb flag works in connection with the select memory bank instruction, smbn. you will recall that the smbn instruction is used to select ram bank 0, 1, 2, 3 or 15 . the smb setting is always contained in the upper four bits of a 12-bit ram address. for this reason, both addressing modes (emb = "0" and emb = "1") apply specifically to the memory bank indicated by the smb instruction, and any restrictions to the addressable area within banks 0, 1, 2, 3 or 15 . direct and indirect 1-bit, 4-bit, and 8-bit addressing methods can be used. several ram locations are addressable at all times, regardless of the current emb flag setting. here are a few guidelines to keep in mind regarding data memory addressing: ? when you address peripheral hardware locations in bank 15, the mnemonic for the memory-mapped hardware component can be used as the operand in place of the actual address location. ? always use an even-numbered ram address as the operand in 8-bit direct and indirect addressing. ? with direct addressing, use the ram address as the instruction operand; with indirect addressing, the instruction specifies a register which contains the operand's address.
addressing modes s3c 72k8/p72k8 3 - 2 notes: 1. 'x' means don't care. 2. blank columns indicate ram areas that are not addressable, given the addressing method and enable memory bank (emb) flag setting shown in the column headers. addressing mode ram areas working registers da da.b @hl @h+da.b @wx @wl mema.b memb.@l emb = 0 emb = 1 emb = 0 emb = 1 x x x bank 0 (general registers and stack) bank 1 (general registers) 000h 01fh 020h 07fh 080h 0ffh 100h 1afh 1b0h smb = 0 smb = 0 bank 15 (peripheral hardware registers) f80h fffh smb = 15 smb = 15 ff0h fb0h fbfh fc0h 1ffh 200h 3ffh 2ffh 300h bank 1 (display registers) bank 2 (general registers) bank 3 (general registers) smb = 3 smb = 1 smb = 1 smb = 1 smb = 1 smb = 2 smb = 2 smb = 3 figure 3- 1. ram address structure
S3C72K8/p72k8 addressing modes 3 - 3 emb and erb initialization values the emb and erb flag bits are set automatically by the values of the reset vector address and the interrupt vector address. when a reset is generated internally, bit 7 of program memory address 0000h is written to the emb flag, initializing it automatically. when a vectored interrupt is generated, bit 7 of the respective vector address table is written to the emb. this automatically sets the emb flag status for the interrupt service routine. when the interrupt is serviced, the emb value is automatically saved to stack and then restored when the interrupt routine has completed. at the beginning of a program, the initial emb and erb flag values for each vectored interrupt must be set by using vent instruction. the emb and erb can be set or reset by bit manipulation instructions (bits, bitr) despite the current smb setting. + + programming tip ? initializing the emb and erb flags the following assembly instructions show how to initialize the emb and erb flag settings: org 0000h ; rom address assignment vent0 1,0, reset ; emb ? 1, erb ? 0, branch reset vent1 0,1,intb ; emb ? 0, erb ? 1, branch intb vent2 0,1,int0 ; emb ? 0, erb ? 1, branch int0 vent3 0,1,int1 ; emb ? 0, erb ? 1, branch int1 vent4 0,1,ints ; emb ? 0, erb ? 1, branch ints vent5 0,1,intt0 ; emb ? 0, erb ? 1, branch intt0 vent6 0,1,intk ; emb ? 0, erb ? 1, branch intk ? ? ? reset bitr emb
addressing modes s3c 72k8/p72k8 3 - 4 enable memory bank settings emb = "1" when the enable memory bank flag emb is set to logic one, you can address the data memory bank specified by the select memory bank (smb) value (0, 1 , 2, 3 or 15) using 1-, 4-, or 8-bit instructions. you can use both direct and indirect addressing modes. the addressable ram areas when emb = "1" are as follows: if smb = 0, 000h?0ffh if smb = 1, 1 0 0h?1ffh if smb = 2, 200h ?2ffh if smb = 3, 300h ?3ffh if smb = 15, f80h?fffh emb = "0" when the enable memory bank flag emb is set to logic zero, the addressable area is defined independently of the smb value, and is restricted to specific locations depending on whether a direct or indirect address mode is used. if emb = "0", the addressable area is restricted to locations 000h?07fh in bank 0 and to locations f80h?fffh in bank 15 for direct addressing. for indirect addressing, only locations 000h?0ffh in bank 0 are addressable, regardless of smb value. to address the peripheral hardware register (bank 15) using indirect addressing, the emb flag must first be set to "1" and the smb value to "15". when a reset occurs, the emb flag is set to the value contained in bit 7 of rom address 0000h. emb-independent addressing at any time, several areas of the data memory can be addressed independent of the current status of the emb flag. these exceptions are described in table 3- 1. table 3- 1. ram addressing not affected by the emb value address addressing method affected hardware program examples 000h?0ffh 4-bit indirect addressing using wx and wl register pairs; 8-bit indirect addressing using sp not applicable ld a,@wx push ea pop ea fb0h?fbfh ff0h?fffh 1-bit direct addressing psw, scmod, iex, irqx, i/o bits emb bitr ie4 fc0h?fffh 1-bit indirect addressing using the l register bsc, i/o btst fc3h.@l band c,p3.@l
S3C72K8/p72k8 addressing modes 3 - 5 select bank register (sb) the select bank register (sb) is used to assign the memory bank and register bank. the 8-bit sb register con sists of the 4-bit select register bank register (srb) and the 4-bit select memory bank register (smb), as shown in figure 3- 2. during interrupts and subroutine calls, sb register contents can be saved to stack in 8-bit units by the push sb instruction. you later restore the value to the sb using the pop sb instruction. smb 3 sb register smb 2 smb 1 smb 0 0 0 srb 1 srb 0 smb (f83h) srb (f82h) figure 3- 2. smb and srb values in the sb register select register bank (srb) instruction the select register bank (srb) value specifies which register bank is to be used as a working register bank. the srb value is set by the 'srb n' instruction, where n = 0, 1, 2, 3. one of the four register banks is selected by the combination of erb flag status and the srb value that is set using the 'srb n' instruction. the current srb value is retained until another register is requested by program software. push sb and pop sb instructions are used to save and restore the contents of srb during interrupts and subroutine calls. reset clears the 4-bit srb value to logic zero. select memory bank (smb) instruction to select one of the four available data memory banks, you must execute an smb n instruction specifying the number of the memory bank you want (0, 1 , 2, 3 or 15). for example, the instruction 'smb 1' selects bank 1 and 'smb 15' selects bank 15. (and remember to enable the selected memory bank by making the appropriate emb flag setting. ) the upper four bits of the 12-bit data memory address are stored in the smb register. if the smb value is not specified by software (or if a reset does not occur) the current value is retained. reset clears the 4-bit smb value to logic zero. the push sb and pop sb instructions save and restore the contents of the smb register to and from the stack area during interrupts and subroutine calls.
addressing modes s3c 72k8/p72k8 3 - 6 direct and indirect addressing 1-bit, 4-bit, and 8-bit data stored in data memory locations can be addressed directly using a specific register or bit address as the instruction operand. indirect addressing specifies a memory location that contains the required direct address. the s3c7 instruction set supports 1-bit, 4-bit, and 8 -bit indirect addressing. for 8-bit indirect addressing, an even-numbered ram address must always be used as the instruction operand. 1-bit addressing table 3- 2. 1-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da.b direct: bit is indicated by the ram address (da), memory bank selection, and specified bit number (b). 0 f80h?fffh bank 15 all 1-bit addressable peripherals (smb = 15) 1 000h?fffh smb = 0-3,15 mema.b direct: bit is indicated by ad - dressable area (mema) and bit number (b). x fb0h?fbfh ff0h?fffh bank 15 is0, is1, emb, erb, iex, irqx, pn.n memb.@l indirect: lower two bits of reg - ister l as indicated by the up - per 10 bits of ram area (memb) and the upper two bits of register l. x fc0h?fffh bank 15 bscn.x pn.n @h + da.b indirect: bit indicated by the lower four bits of the address (da), memory bank selection, and the h register identifier. 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0-3,15 all 1-bit addressable peripherals (smb = 15) note : 'x' means don't care.
S3C72K8/p72k8 addressing modes 3 - 7 + + programming tip ? 1-bit addressing modes 1-bit direct addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; f85h.3 ? 1 btst cflag ; if fbah.0 = 1, skip bits bflag ; else if, fbah.0 = 0, f85h.3 (bmod.3) ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 bits aflag ; 34h.3 ? 1 bits bflag ; 85h.3 ? 1 btst cflag ; if 0bah.0 = 1, skip bits bflag ; else if 0bah.0 = 0, 085h.3 ? 1 bits p3.0 ; ff3h.0 (p3.0) ? 1 1-bit indirect addressing 1. if emb = "0": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, fbah.0 ? 1 2. if emb = "1": aflag equ 34h.3 bflag equ 85h.3 cflag equ 0bah.0 smb 0 ld h,#0bh ; h ? #0bh btstz @h+cflag ; if 0bah.0 = 1, 0bah.0 ? 0 and skip bits cflag ; else if 0bah.0 = 0, 0bah.0 ? 1
addressing modes s3c 72k8/p72k8 3 - 8 4-bit addressing table 3- 3. 4-bit direct and indirect ram addressing operand notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da direct: 4-bit address indicated by the ram address (da) and the memory bank selection 0 f80h?fffh bank 15 all 4-bit ad dressable pe ripherals 1 000h?fffh smb = 0-3,15 (smb = 15) @hl indirect: 4-bit address indi - cated by the memory bank selection and register hl 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0-3,15 all 4-bit ad dressable pe ripherals (smb = 15) @wx indirect: 4-bit address indi - cated by register wx x 000h?0ffh bank 0 ? @wl indirect: 4-bit address indi - cated by register wl x 000h?0ffh bank 0 note : ' x ' means don't care. + + programming tip ? 4-bit addressing modes 4-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh smb 15 ; non-essential instruction, since emb = "0" ld a,p3 ; a ? (p3) smb 0 ; non-essential instruction, since emb = "0" ld adata,a ; (046h) ? a ld bdata,a ; (f8eh (lcon)) ? a 2. if emb = "1": ] adata equ 46h bdata equ 8eh smb 15 ld a,p3 ; a ? (p3) smb 0 ld adata,a ; (046h) ? a ld bdata,a ; (08eh) ? a
S3C72K8/p72k8 addressing modes 3 - 9 + + programming tip ? 4-bit addressing modes 4-bit indirect addressing (example 1) 1. if emb = "0", compare bank 0 locations 040h?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 0 (060h?066h) = a, skip sret decs l jr comp ret 2 . if emb = " 1 ", compare bank 0 locations 040h?046h with bank 1 locations 1 60h ?1 66h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata comp ld a,@wl ; a ? bank 0 (040h?046h) cpse a,@hl ; if bank 1 (160h?166h) = a, skip sret decs l jr comp ret 4-bit indirect addressing (example 2) 1. if emb = "0", exchange bank 0 locations 040h?046h with bank 0 locations 060h?066h: adata equ 46h bdata equ 66h smb 1 ; non-essential instruction, since emb = "0" ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; if bank 0 (060h?066h) ? a, skip jr trans 2 . if emb = " 1 ", exchange bank 0 locations 040h?046h with bank 1 locations 1 60h ?1 66h: adata equ 46h bdata equ 66h smb 1 ld hl,#bdata ld wx,#adata trans ld a,@wl ; a ? bank 0 (040h?046h) xchd a,@hl ; if bank 1 (160h?166h) ? a, skip jr trans
addressing modes s3c 72k8/p72k8 3 - 10 8-bit addressing table 3- 4. 8-bit direct and indirect ram addressing instruction notation addressing mode description emb flag setting addressable area memory bank hardware i/o mapping 000h?07fh bank 0 ? da direct: 8-bit address indicated by the ram address ( da = even number ) and memory bank selection 0 f80h?fffh bank 15 all 8-bit ad dressable pe ripherals 1 000h?fffh smb = 0-3,15 (smb = 15) @hl indirect: the 8-bit address indi - cated by the memory bank selection and register hl; (the 4 -bit l register value must be an even number) 0 000h?0ffh bank 0 ? 1 000h?fffh smb = 0-3,15 all 8-bit ad dressable pe ripherals (smb = 15)
S3C72K8/p72k8 addressing modes 3 - 11 + + programming tip ? 8-bit addressing modes 8-bit direct addressing 1. if emb = "0": adata equ 46h bdata equ 8eh ; non-essential instruction, since emb = "0" smb 15 ld ea , p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (f8eh) ? a, (f8fh) ? e 2. if emb = "1": adata equ 46h bdata equ 8eh smb 15 ld ea ,p4 ; e ? (p5), a ? (p4) smb 0 ld adata,ea ; (046h) ? a, (047h) ? e ld bdata,ea ; (08eh) ? a, (08fh) ? e 8-bit indirect addressing 1. if emb = "0": adata equ 46h smb 1 ; non-essential instruction, since emb = "0" ld hl,#adata ld ea,@hl ; a ? (046h), e ? (047h) 2 . if emb = " 1 ": adata equ 46h smb 1 ld hl,#adata ld ea,@hl ; a ? ( 1 46h), e ? ( 1 47h)
S3C72K8/p72k8 memory map 4 - 1 4 memory map overview to support program control of peripheral hardware, i/o addresses for peripherals are memory-mapped to bank 15 of the ram. memory mapping lets you use a mnemonic as the operand of an instruction in place of the specific memory location. access to bank 15 is controlled by the select memory bank (smb) instruction and by the enable memory bank flag (emb) setting. if the emb flag is "0", bank 15 can be addressed using direct addressing, regardless of the current smb value. 1-bit direct and indirect addressing can be used for specific locations in bank 15, regardless of the current emb value. i/o map for hardware registers table 4- 1 contains detailed information about i/o mapping for peripheral hardware in bank 15 (register loca tions f80h?fffh). use the i/o map as a quick-reference source when writing application programs. the i/o map gives you the following information: ? register address ? register name (mnemonic for program addressing) ? bit values (both addressable and non- manipulable) ? read-only, write-only, or read and write addressability ? 1-bit, 4-bit, or 8-bit data manipulation characteristics
memory map S3C72K8/p72k8 4 - 2 table 4- 1. i/o map for memory bank 15 addressing symbol description affected memory mapped i/o 1 - bit direct addressing da.b the bit indicated by memory bank, da and bit. (emb=0, or emb=1 and smb 15) all peripheral hardware that can be manipulated in 1 bit. 4 - bit direct addressing da the address indicated by memory bank and da. (emb=0, or emb=1 and smb 15) all peripheral hardware that can be manipulated in 4 bits. 8 - bit direct addressing da the address (da specifies an even address) indicated by memory bank and da. (emb=0, or emb=1 and smb 15) all peripheral hardware that can be manipulated in 8 bits. 4 - bit indirect addressing @hl the address indicated by memory bank and hl register. (emb=1 and smb 15) all peripheral hardware that can be manipulated in 4 bits. 8 - bit indirect addressing @hl the address indicated by memory bank and hl (the contents of the l register are even). (emb=1 and smb 15) all peripheral hardware that can be manipulated in 8 bit. 1 - bit manipulating addressing mema.b the bit indicated by mema and bit. (regardless of the status of emb and smb) is0, is1, emb, erb, iex, irqx, pn.m memb.@ l the bit indicated by the lower 2 bits of the l register of the address indicated by the upper 10 bits of memb and the upper 2 bits of the l reigster. (regardless of the status of emb and smb) pn.m @h+da.b the bit of the address indicated by memory bank, h register and the lower 4 bits of da. (emb=1 and smb=15) all peripheral hardware that can be manipulated in 1 bit.
S3C72K8/p72k8 memory map 4 - 3 table 4- 1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit f80h sp .3 .2 .1 "0" r/w no no yes f81h .7 .6 .5 .4 f82h f83h f84h f85h bmod .3 .2 .1 .0 w .3 yes no f86h bcnt r no no yes f87h f88h wmod .3 .2 .1 .0 w .3 no yes f89h .7 "0" .5 .4 f8ah f8bh f8ch lmod .3 .2 .1 .0 w no no yes f8dh .7 .6 .5 .4 f8eh lcon "0" .2 .1 .0 w no yes no f8fh f90h tmod0 .3 .2 "0" "0" w .3 no yes f91h "0" .6 .5 .4 f92h "0" toe0 "0" "0" r/w yes yes no f93h f94h tcnt0 r no no yes f95h f96h tref0 w no no yes f97h f98h wdmod .3 .2 .1 .0 w no no yes f99h .7 .6 .5 .4 f9ah wdflag wdtcf "0" "0" "0" w .3 yes no fa6h pne1 .3 .2 .1 .0 w no yes yes fa7h fa8h pne2 .3 .2 .1 .0 w no no yes fa9h .7 .6 .5 .4 faah pne3 "0" .2 .1 .0 yes no ? ? ?
memory map S3C72K8/p72k8 4 - 4 table 4- 1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fb0h psw is1 is0 emb erb r/w yes yes yes fb1h c ( 1 ) sc2 sc1 sc0 r no no fb2h ipr ime .2 .1 .0 w ime yes no fb3h pcon .3 .2 .1 .0 w no yes no fb4h imod0 "0" "0" .1 .0 w no yes no fb5h imod1 "0" "0" "0" .0 w no yes no fb6h imodk "0" .2 .1 .0 w no yes no fb7h scmod .3 .2 "0" .0 w yes no no fb8h it0 ie4 irq4 ieb irqb r/w yes yes no fb9h fbah it1 "0" "0" iew irqw r/w yes yes no fbbh it2 "0" "0" iek irq k fbch it3 "0" "0" iet0 irqt0 fbdh it4 "0" "0" ies irqs fbeh it5 ie1 irq1 ie0 irq0 fbfh it6 "0" "0" ie2 irq2 fc0h bsc0 r/w yes yes yes fc1h bsc1 fc2h bsc2 yes fc3h bsc3 ? ? ? fd0h clmod .3 "0" .1 .0 w no yes no fd 1 h fd 2 h fd 3 h fd 4 h cmpreg .3 .2 .1 .0 r no yes no fd5h fd6h cmod .3 .2 .1 .0 r/ w no no yes fd7h .7 .6 .5 "0" fd8h fd9h
S3C72K8/p72k8 memory map 4 - 5 table 4- 1. i/o map for memory bank 15 (continued) memory bank 15 addressing mode address register bit 3 bit 2 bit 1 bit 0 r/w 1-bit 4-bit 8-bit fdah imod2 .3 "0" .1 .0 w no yes no fdbh fdch pumod1 .3 .2 "0" .0 w no no yes fddh "0" "0" "0" .4 fdeh pumod2 .3 .2 .1 .0 w no yes no fdfh fe0h smod .3 .2 .1 .0 w .3 no yes fe1h .7 .6 .5 "0" fe2h p1mod "0" "0" .1 .0 w no yes no fe3h fe4h sbuf r/w no no yes fe5h fe6h pmg 1 .3 .2 .1 .0 w no no yes fe7h "0" .6 .5 .4 fe8h pmg 2 .3 .2 .1 .0 w no no yes fe9h .7 .6 .5 .4 ? ff0h port 0 .3 .2 .1 .0 r/w yes yes no ff1h port 1 .3 .2 .1 .0 r yes yes no ff2h port 2 .3 .2 .1 .0 r/w yes yes yes ff3h port 3 .3 /.7 .2/.6 .1/.5 .0/.4 ff4h port 4 "0" .2 .1 .0 r/w yes yes no ? ? ff f h notes: 1. the carry flag can be read or written by specific bit manipulation instructions only. 2. p5 is mapped at ram locations 1f0h-1ffh. (refer to 12-13 page)
memory map S3C72K8/p72k8 4 - 6 register descriptions in this section, register descriptions are presented in a consistent format to familiarize you with the memory- mapped i/o locations in bank 15 of the ram. figure 4- 1 describes features of the register description format. register descriptions are arranged in alphabetical order. programmers can use this section as a quick-reference source when writing application programs. counter registers, buffer registers, and reference registers, as well as the stack pointer and port i/o latches, are not included in these descriptions. more detailed information about how these registers are used is included in part ii of this manual, "hardware descriptions " , in the context of the corresponding peripheral hardware module descriptions.
S3C72K8/p72k8 memory map 4 - 7 clmod - clock output mode control register clmod.3 enable/disable clock output control bit clmod.2 bit 2 0 always logic zero clmod.1 - .0 clock source and frequency selection control bits 3 2 1 0 bit identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 r = read-only w = write-only r/w = read/write bit value immediately after a reset bit number in msb to lsb order type of addressing that must be used to address the bit (1-bit, 4-bit, or 8-bit) description of the effect of specific bit settings bit identifier used for bit addressing register and bit ids used for bit addressing cpu fd0h associated hardware module register location in ram bank 15 name of individual bit or related bits register name register id select cpu clock souce fx/4, fx/8, fx/64 (1.05 mhz, 524khz, or 65.5 khz), or fxt/4 select system clock fxx/8 (524 khz at 4.19 mhz) select system clock fxx/16 (262 khz at 4.19 mhz) select system clock fxx/64 (65.5 khz at 4.19 mhz) 0 0 1 1 0 1 0 1 0 disable clock output at the clo pin 0 enable clock output at the clo pin figure 4- 1. register description format
memory map S3C72K8/p72k8 4 - 8 bmod ? basic timer mode register bt f85h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 bmod.3 basic timer restart bit 1 restart basic timer, then clear irqb flag, bcnt and bmod.3 to logic zero bmod.2 ?.0 input clock frequency and signal stabilization interval control bits 0 0 0 input clock frequency: interrupt interval time (wait time) : fxx / 2 12 (1.02 khz) 2 20 / fxx (250 ms) 0 1 1 input clock frequency: interrupt interval time (wait time) : fxx / 2 9 (8.18 khz) 2 17 / fxx (31.3 ms) 1 0 1 input clock frequency: interrupt interval time (wait time) : fxx / 2 7 (32.7 khz) 2 15 / fxx (7.82 ms) 1 1 1 input clock frequency: interrupt interval time (wait time) : fxx / 2 5 (131 khz) 2 13 / fxx (1.95 ms) notes : 1. when a reset occurs, the oscillation stabilization time is 31.3 ms (2 17 / fxx) at 4.19 mhz. . 2. ' fxx' is the system clock rate given a clock frequency of 4.19 mhz.
S3C72K8/p72k8 memory map 4 - 9 clmod ? clock output mode register cpu fd0h bit 3 2 1 0 identifier .3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 clmod.3 enable/disable clock output control bit 0 disable clock output at the clo pin 1 enable clock output at the clo pin clmod.2 bit 2 0 always logic zero clmod.1?.0 clock source and frequency selection control bits 0 0 select cpu clock source fx x /4, fx x/8 or f x x/64 (1.05 mhz, 524 khz or 65.5 khz) ; refer to pcon 0 1 select clock f x x/8 (524 khz) 1 0 select clock fxx/16 (262 khz) 1 1 select clock fxx/64 (65.5 khz ) note : " fx" is the main clock, given a clock frequency of 4.19 mhz.
memory map S3C72K8/p72k8 4 - 10 cmod ? comparator mode register comparator fd 7 h , fd6h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 "0" .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write r/ w r/ w r/ w r/ w r/ w r/ w r/ w r/ w bit addressing 8 8 8 8 8 8 8 8 .7 comparator enable/disable bit 0 comparator operation disable 1 comparator operation enable .6 conversion timer control bit 0 4 2 8 /fx, 244.4 m s at 4.19 mhz 1 4 2 5 /fx, 30.5 m s at 4.19 mhz .5 external/internal reference selection bit 0 internal reference, cin0?1; analog input 1 external reference at cin0, cin1; analog input .4 bit 4 0 always logic zero .3?.0 reference voltage selection bits selected v ref = v dd (n+0.5) 16 , n = 0 to 15
S3C72K8/p72k8 memory map 4 - 11 ie0, irq0 ? int0 interrupt enable/request flags cpu fbeh ie1 , irq1 ? int1 interrupt enable/request flags cpu fbeh bit 3 2 1 0 identifier ie1 irq1 ie0 irq0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie1 int1 interrupt enable flag 0 disable interrupt requests at the int1 pin 1 enable interrupt requests at the int1 pin irq1 int1 interrupt request flag ? generate int1 interrupt (this bit is set and cleared by hardware when rising or falling edge detected at int1 pin.) ie0 int0 interrupt enable flag 0 disable interrupt requests at the int0 pin 1 enable interrupt requests at the int0 pin irq0 int0 interrupt request flag ? generate int0 interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at int0 pin.)
memory map S3C72K8/p72k8 4 - 12 ie2 , irq2 ? int2 interrupt enable/request flags cpu fbfh bit 3 2 1 0 identifier "0" "0" ie2 irq2 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 ?.2 bits 3?2 0 always logic zero ie2 int2 interrupt enable flag 0 disable int2 interrupt requests at the int2 pin 1 enable int2 interrupt requests at the int2 pin irq2 int2 interrupt request flag ? generate int2 quasi-interrupt (this bit is set and is not cleared automatically by hardware when a rising or falling edge is detected at int2. since int2 is a quasi-interrupt, irq2 flag must be cleared by software.)
S3C72K8/p72k8 memory map 4 - 13 ie4 , irq4 ? int4 interrupt enable/request flags cpu fb8h ieb, irqb ? intb interrupt enable/request flags cpu fb8h bit 3 2 1 0 identifier ie4 irq4 ieb irqb reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 ie4 int4 interrupt enable flag 0 disable interrupt requests at the int4 pin 1 enable interrupt requests at the int4 pin irq4 int4 interrupt request flag ? generate int4 interrupt (this bit is set and cleared automatically by hardware when rising and falling signal edge detected at int4 pin.) ieb intb interrupt enable flag 0 disable intb interrupt requests 1 enable intb interrupt requests irqb intb interrupt request flag ? generate intb interrupt (this bit is set and cleared automatically by hardware when reference interval signal received from basic timer.)
memory map S3C72K8/p72k8 4 - 14 ies , irqs ? ints interrupt enable/request flags cpu fbdh bit 3 2 1 0 identifier "0" "0" ies irqs reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3?.2 bits 3?2 0 always logic zero ies ints interrupt enable flag 0 disable ints interrupt requests 1 enable ints interrupt requests irqs ints interrupt request flag ? generate ints interrupt (this bit is set and cleared automatically by hardware when serial data transfer completion signal received from serial i/o interface.)
S3C72K8/p72k8 memory map 4 - 15 iet0 , irqt0 ? intt0 interrupt enable/request flags cpu fbch bit 3 2 1 0 identifier "0" "0" iet0 irqt0 reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 ? 1/4 1/4 .3?.2 bits 3?2 0 always logic zero iet0 intt0 interrupt enable flag 0 disable intt0 interrupt requests 1 enable intt0 interrupt requests irqt0 intt0 interrupt request flag ? generate intt0 interrupt (this bit is set and cleared automatically by hardware when contents of tcnt0 and tref0 registers match.)
memory map S3C72K8/p72k8 4 - 16 iek, irqk ? intk interrupt enable/request flags cpu fbbh bit 3 2 1 0 identifier "0" "0" iek irq k reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 iek intk interrupt enable flag 0 disable interrupt requests at the k0?k 3 pins 1 enable interrupt requests at the k0?k 3 pins irqk intk interrupt request flag ? generate intk interrupt (this bit is set and cleared automatically by hardware when rising or falling edge detected at k0?k 3 pins.)
S3C72K8/p72k8 memory map 4 - 17 iew , irqw ? intw interrupt enable/request flags cpu fbah bit 3 2 1 0 identifier "0" "0" iew irqw reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 ? .3?.2 bits 3?2 0 always logic zero iew intw interrupt enable flag 0 disable intw interrupt requests 1 enable intw interrupt requests irqw intw interrupt request flag ? generate intw interrupt (this bit is set when the timer interval is set to 0.5 seconds or 3.91 milliseconds.) note : since intw is a quasi-interrupt, the irqw flag must be cleared by software.
memory map S3C72K8/p72k8 4 - 18 imod0 ? external interrupt 0 (int0) mode register cpu fb4h bit 3 2 1 0 identifier 3 "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod0. 3 interrupt sampling clock selection bit 0 select cpu clock as a sampling clock 1 select sampling clock frequency of the selected system clock (fxx/64) imod0. 2 bit 2 0 always logic zero imod0.1?.0 external interrupt mode control bits 0 0 interrupt requests are triggered by a rising signal edge 0 1 interrupt requests are triggered by a falling signal edge 1 0 interrupt requests are triggered by both rising and falling signal edges 1 1 interrupt request flag (irqx) cannot be set to logic one
S3C72K8/p72k8 memory map 4 - 19 imod 1 ? external interrupt 1 (int 1 ) mode register cpu fb 5 h bit 3 2 1 0 identifier "0" "0" "0" imod1.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod1.3?.1 bits 3?1 0 always logic zero imod1.0 external interrupt 1 edge detection control bit 0 rising edge detection 1 falling edge detection
memory map S3C72K8/p72k8 4 - 20 imod2 ? external interrupt 2 (int2) mode register cpu f da h bit 3 2 1 0 identifier "0" "0" "0" imod2.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imod2.3?.1 bits 3?1 0 always logic zero imod2.0 external interrupt 2 edge detection selection bit 0 interrupt request at int2 pin trigged by rising edge 1 interrupt request at int2 pin trigged by falling edge
S3C72K8/p72k8 memory map 4 - 21 imodk ? external key interrupt mode register cpu fb6h bit 3 2 1 0 identifier "0" imodk.2 imodk.1 imodk.0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 imodk.3 bit 3 0 always logic zero imodk.2 external key interrupt edge detection selection bit 0 falling edge detection 1 rising edge detection imodk.1?.0 external key interrupt mode control bits 0 0 disable key interrupt 0 1 enable edge detection at k0 ?k1 pins 1 0 enable edge detection at k 0? k 2 pins 1 1 enable edge detection at k0 ? k 3 pins notes: 1. to generate a key interrupt, the selected pins must be configured to input mode. 2. if any one of key interrupt pins selected by imodk register is configured as output mode, only falling edge can be detected. 3. to generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. and then, select edge detection and pins by setting imodk register.
memory map S3C72K8/p72k8 4 - 22 ipr ? interrupt priority register cpu fb2h bit 3 2 1 0 identifier ime .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1/4 4 4 4 ime interrupt master enable bit 0 disable all interrupt processing 1 enable processing for all interrupt service requests ipr.2?.0 interrupt priority assignment bits 0 0 0 process all interrupt requests at low priority 0 0 1 process intb and int4 interrupts only 0 1 0 process int0 interrupts only 0 1 1 process int1 interrupts only 1 0 0 process ints interrupts only 1 0 1 process intt0 interrupts only 1 1 0 process intk interrupts only
S3C72K8/p72k8 memory map 4 - 23 lcon ? lcd output control register lcd f8eh bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 lcon.3 lcd bais selection bit 0 1/4 bias select 1 1/3 bias select lcon.2 lcd clock output disable/enable bit 0 disable lcdck and lcdsy signal outputs 1 enable lcdck and lcdsy signal outputs lcon.1 bit 1 0 lcd display off ( all com/seg pins are high output) 1 lcd display on lcon.0 bit 0 0 turn off the internal lcd bias tr 1 turn on the internal lcd bias tr note s : 1. in case of lcon.0, you can turn on/off internal lcd bias tr. 2. in case of internal lcd bias when lcon.1?.0 = #00b, lcd display is turned off. when lcon.1?.0 = #11b, lcd display is turned on. 3. in case of external lcd bias when lcon.1?.0 = #00b and v lc5 = "high", lcd display is turned off. when lcon.1?.0 = #10b and v lc5 = "low", lcd display is turned on. 4. to select lcd bi as, you must use both the lcon.3 setting and an external lcd bias circuit connection.
memory map S3C72K8/p72k8 4 - 24 lmod ? lcd mode register lcd f8dh, f8ch bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 lmod.7?. 6 lcd output segment and pin configuration bits 0 0 segments 32?35 and 36?39 0 1 segment 36?39; 1-bit output at p5.0?p5.3 1 0 segment 32?35; 1-bit output at p5.4?p5.7 1 1 1-bit output only at p5.0?p5.7 lmod. 5 ?. 4 lcd clock (lcdck) frequency selection bits 0 0 when 1/ 3 duty: f w/ 2 8 ( 128 hz); when 1/ 4 duty: f w/ 2 7 ( 256 hz) ; when 1/8 duty: f w /2 6 (512 hz) 0 1 when 1/ 3 duty: f w/ 2 7 ( 256 hz); when 1/ 4 duty: f w/ 2 6 ( 512 hz) ; when 1/8 duty: f w/ 2 5 (1024 hz) 1 0 when 1/ 3 duty: f w/ 2 6 ( 512 hz); when 1/ 4 duty: f w/ 2 5 ( 1024 hz) ; when 1/8 duty: f w/ 2 4 (2048 hz) 1 1 when 1/ 3 duty: f w/ 2 5 ( 1024 hz); when 1/ 4 duty: f w/ 2 4 ( 2048 hz) ; when 1/8 duty: f w/ 2 3 (4096 hz) lmod. 3 ?. 2 lcd output segment and pin configuration bits 0 0 1/8 duty (com0?com7 select) 1 0 1/ 4 duty (com0?com3 select) 1 1 1/ 3 duty (com0?com2 select) lmod.1 ?.0 lcd display mode selection bits 0 0 all lcd dots off 0 1 all lcd dots on 1 1 normal display note: fw = 32,768 khz
S3C72K8/p72k8 memory map 4 - 25 pcon ? power control register cpu fb3h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pcon.3?.2 cpu operating mode control bits 0 0 enable normal cpu operating mode 0 1 initiate idle power-down mode 1 0 initiate stop power-down mode pcon.1?.0 cpu clock frequency selection bits 0 0 if scmod.0 = "0" , fx/64; if scmod.0 = "1", fxt/ 4 1 0 if scmod.0 = "0", fx/8; if scmod.0 = "1", fxt/ 4 1 1 if scmod.0 = "0", fx/4; if scmod.0 = "1", fxt/4 note: ' fx' is the main system clock; ' fxt' is the subsystem clock.
memory map S3C72K8/p72k8 4 - 26 pmg1 ? port i/o mode flags (group 1: ports 0, 4 ) i/o fe 7 h, fe 6 h bit 7 6 5 4 3 2 1 0 identifier "0" pm 4 .2 pm 4 .1 pm 4 .0 pm0.3 pm0.2 pm0.1 pm0.0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 bit 7 0 always logic zero pm 4 .2 p 4 .2 i/o mode selection flag 0 set p 4 .2 to input mode 1 set p 4 .2 to output mode pm 4 .1 p 4 .1 i/o mode selection flag 0 set p 4 .1 to input mode 1 set p 4 .1 to output mode pm 4 .0 p 4 .0 i/o mode selection flag 0 set p 4 .0 to input mode 1 set p 4 .0 to output mode pm0.3 p0.3 i/o mode selection flag 0 set p0.3 to input mode 1 set p0.3 to output mode pm0.2 p0.2 i/o mode selection flag 0 set p0.2 to input mode 1 set p0.2 to output mode pm0.1 p0.1 i/o mode selection flag 0 set p0.1 to input mode 1 set p0.1 to output mode pm0.0 p0.0 i/o mode selection flag 0 set p0.0 to input mode 1 set p0.0 to output mode
S3C72K8/p72k8 memory map 4 - 27 pmg2 ? port i/o mode flags (group 2: port s 2, 3 ) i/o fe 9 h, fe 8 h bit 7 6 5 4 3 2 1 0 identifier pm3.3 pm 3 .2 pm 3 .1 pm 3 .0 pm 2 .3 pm 2 .2 pm 2 .1 pm 2 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pm3.3 p3.3 i/o mode selection flag 0 set p3.3 to input mode 1 set p3.3 to output mode pm 3.2 p 3.2 i/o mode selection flag 0 set p 3.2 to input mode 1 set p 3.2 to output mode pm 3.1 p 3.1 i/o mode selection flag 0 set p 3.1 to input mode 1 set p 3.1 to output mode pm 3.0 p 3.0 i/o mode selection flag 0 set p 3.0 to input mode 1 set p 3.0 to output mode pm 2 .3 p 2 .3 i/o mode selection flag 0 set p 2 .3 to input mode 1 set p 2 .3 to output mode pm 2 .2 p 2 .2 i/o mode selection flag 0 set p 2 .2 to input mode 1 set p 2 .2 to output mode pm 2 .1 p 2 .1 i/o mode selection flag 0 set p 2 .1 to input mode 1 set p 2 .1 to output mode pm 2 .0 p 2 .0 i/o mode selection flag 0 set p 2 .0 to input mode 1 set p 2 .0 to output mode
memory map S3C72K8/p72k8 4 - 28 p 1 m od ? port 1 mode register i/o fe 2 h bit 3 2 1 0 identifier "0" "0" .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 and .2 bits 3?2 0 always logic zero p1mod.1 p1.1 analog/digital selection bit 0 configure p1.1 as an analog input pin 1 configure p1.1 as a digital input pin (interrupt may be occurred) p1mod.0 p1.0 analog/digital selection bit 0 configure p1.0 as an analog input pin 1 configure p1.0 as a digital input pin (interrupt may be occurred) note: if analog input is selected in state if digital input, the irq0 and irq1 flags are set automatically.
S3C72K8/p72k8 memory map 4 - 29 pne1 ? n-channel open-drain mode register 1 i/o f a6 h bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pne0.3 p 0 . 3 n-channel open-drain configurable bit 0 configure p0.3 as a push-pull 1 configure p0.3 as a n-channel open-drain pne0.2 p 0 .2 n-channel open-drain configurable bit 0 configure p 0 .2 as a push-pull 1 configure p 0 .2 as a n-channel open-drain pne0.1 p 0 .1 n-channel open-drain configurable bit 0 configure p 0 .1 as a push-pull 1 configure p 0 .1 as a n-channel open-drain pne0.0 p 0 .0 n-channel open-drain configurable bit 0 configure p 0 .0 as a push-pull 1 configure p 0 .0 as a n-channel open-drain
memory map S3C72K8/p72k8 4 - 30 pne2 ? n-channel open-drain mode register 2 i/o fa9h, f a 8h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 pne2.7 p3.3 n-channel open-drain configurable bit 0 configure p 3.3 as a push-pull 1 configure p 3.3 as a n-channel open-drain pne2.6 p 3.2 n-channel open-drain configurable bit 0 configure p 3.2 as a push-pull 1 configure p 3.2 as a n-channel open-drain pne2.5 p 3.1 n-channel open-drain configurable bit 0 configure p 3.1 as a push-pull 1 configure p 3.1 as a n-channel open-drain pne2.4 p 3.0 n-channel open-drain configurable bit 0 configure p 3.0 as a push-pull 1 configure p 3.0 as a n-channel open-drain pne2.3 p 2.3 n-channel open-drain configurable bit 0 configure p 2 .3 as a push-pull 1 configure p 2 .3 as a n-channel open-drain pne2.2 p 2.2 n-channel open-drain configurable bit 0 configure p 2 .2 as a push-pull 1 configure p 2 .2 as a n-channel open-drain pne2.1 p 2.1 n-channel open-drain configurable bit 0 configure p 2 .1 as a push-pull 1 configure p 2 .1 as a n-channel open-drain pne2.0 p 2.0 n-channel open-drain configurable bit 0 configure p 2 .0 as a push-pull 1 configure p 2 .0 as a n-channel open-drain
S3C72K8/p72k8 memory map 4 - 31 pne 3 ? n-channel open-drain mode register 3 i/o faah bit 3 2 1 0 identifier "0" .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 .3 bit 3 0 always logic zero pne3.2 p 4.2 n-channel open-drain configurable bit 0 configure p 4.2 as a push-pull 1 configure p 4.2 as a n-channel open-drain pne3 .1 p 4.1 n-channel open-drain configurable bit 0 configure p 4.1 as a push-pull 1 configure p 4.1 as a n-channel open-drain pne3 .0 p 4.0 n-channel open-drain configurable bit 0 configure p 4.0 as a push-pull 1 configure p 4.0 as a n-channel open-drain
memory map S3C72K8/p72k8 4 - 32 psw ? program status word cpu fb1h, fb0h bit 7 6 5 4 3 2 1 0 identifier c sc2 sc1 sc0 is1 is0 emb erb reset reset value (1) 0 0 0 0 0 0 0 read/write r/w r r r r/w r/w r/w r/w bit addressing (2) 8 8 8 1/4 /8 1/4 /8 1/4 /8 1/4 /8 c carry flag 0 no overflow or borrow condition exists 1 an overflow or borrow condition does exist sc2?sc0 skip condition flags 0 no skip condition exists; no direct manipulation of these bits is allowed 1 a skip condition exists; no direct manipulation of these bits is allowed is1, is0 interrupt status flags 0 0 service all interrupt requests 0 1 service only the high-priority interrupt(s) as determined in the interrupt priority register (ipr) 1 0 do not service any more interrupt requests 1 1 undefined emb enable data memory bank flag 0 restrict program access to data memory to bank 15 (f80h?fffh) and to the locations 000h ? 07fh in the bank 0 only 1 enable full access to data memory banks 0 , 1, 2 and 15 erb enable register bank flag 0 select register bank 0 as working register area 1 select register banks 0, 1, 2 or 3 as working register area in accordance with the select register bank (srb) instruction operand notes : 1. the value of the carry flag after a reset occurs during normal operation is undefined. if a reset occurs during power-down mode (idle or stop), the current value of the carry flag is retained. 2. the carry flag can only be addressed by a specific set of 1-bit manipulation instructions. see section 2 for detailed information.
S3C72K8/p72k8 memory map 4 - 33 pumod1 ? pull- u p resistor mode register 1 i/o fddh, fdch bit 7 6 5 4 3 2 1 0 identifier "0" "0" "0" pur4 pur3 pur2 "0" pur0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7?.5 bits 7?5 0 always logic zero pur4 connect/disconnect port 4 pull- u p resistor control bit 0 disconnect port 4 pull-up resistor 1 connect port 4 pull-up resistor pur3 connect/disconnect port 3 pull- u p resistor control bit 0 disconnect port 3 pull-up resistor 1 connect port 3 pull-up resistor pur2 connect/disconnect port 2 pull- u p resistor control bit 0 disconnect port 2 pull-up resistor 1 connect port 2 pull-up resistor .1 bit 1 0 always logic zero pur0 connect/disconnect port 0 pull- u p resistor control bit 0 disconnect port 0 pull-up resistor 1 connect port 0 pull-up resistor
memory map S3C72K8/p72k8 4 - 34 pumod2 ? pull- u p resistor mode register 2 i/o fdeh bit 3 2 1 0 identifier .3 .2 .1 .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 4 4 4 4 pu mod2.3 connect/disconnect p1.3 pull- u p resistor control bit 0 disconnect p1.3 pull-up resistor 1 connect p1.3 pull-up resistor pu mod2.2 connect/disconnect p 1.2 pull- u p resistor control bit 0 disconnect p1.2 pull-up resistor 1 connect p1.2 pull-up resistor pu mod2.1 connect/disconnect p 1.1 pull- u p resistor control bit 0 disconnect p1.1 pull-up resistor 1 connect p1.1 pull-up resistor pu mod2.0 connect/disconnect p 1.0 pull- u p resistor control bit 0 disconnect p1.0 pull-up resistor 1 connect p1.0 pull-up resistor
S3C72K8/p72k8 memory map 4 - 35 scmod ? system clock mode control register cpu fb7h bit 3 2 1 0 identifier .3 .2 "0" .0 reset reset value 0 0 0 0 read/write w w w w bit addressing 1 1 1 1 scmod. 3 bit 3 0 enable main system clock 1 disable main system clock scmod. 2 bit 2 0 enable sub system clock 1 disable sub system clock scmod. 1 bit 1 0 always logic zero scmod. 0 bit 0 0 select main system clock 1 select sub system clock note s : 1. sub-oscillation goes into stop mode only by scmod.2. pcon which revokes stop mode cannot stop the sub- oscillation. 2. you can use scmod.2 as follows (ex; after data bank was used, a few minutes have passed): main operation ? sub-operation ? sub-idle (lcd on, after a few minutes later without any external input) ? sub- operation ? main operation ? scmod.2 = 1 ? main stop mode (lcd off). 3. scmod bits 3 ? 0 cannot be modified simultaneously by a 4-bit instruction; they can only be modified by separate 1-bit instructions.
memory map S3C72K8/p72k8 4 - 36 smod ? serial i/o mode register sio fe1h, fe0h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 "0" .3 .2 .1 .0 reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 smod.7?.5 serial i/o clock selection and sbuf r/w status control bits 0 0 0 use an external clock at the sck pin; enable sbuf when sio operation is halted or when sck goes high 0 0 1 use the tol 0 clock from timer/counter 0 ; enable sbuf when sio operation is halted or when sck goes high 0 1 x use the selected cpu clock (fx/4, fx/ 8, fx/ 64 , or fxt/4 ) then, enable sbuf read/write operation. 'x' means 'don't care.' 1 0 0 4.09 khz clock (fxx/2 10 ) 1 1 1 262 khz clock (fxx/2 4 ); n ote : you cannot select a fx/2 4 clock frequency if you have selected a cpu clock of fx x /64 note: all khz frequency ratings assume a system clock of 4.19 mhz. smod.4 bit 4 0 always logic zero smod.3 initiate serial i/o operation bit 1 clear irqs flag and 3-bit clock counter to logic zero; then initiate serial trans - mission. when sio transmission starts, this bit is cleared by hardware to logic zero smod.2 enable/disable sio data shifter and clock counter bit 0 disable the data shifter and clock counter; the contents of irqs flag is retained when serial transmission is completed 1 enable the data shifter and clock counter; the irqs flag is set to logic one when serial transmission is completed smod.1 serial i/o transmission mode selection bit 0 receive-only mode 1 transmit-and-receive mode smod.0 lsb/msb transmission mode selection bit 0 transmit the most significant bit (msb) first 1 transmit the least significant bit (lsb) first
S3C72K8/p72k8 memory map 4 - 37 tmod0 ? timer/counter 0 mode register t/c0 f91h, f90h bit 7 6 5 4 3 2 1 0 identifier "0" .6 .5 .4 .3 .2 "0" "0" reset reset value 0 0 0 0 0 0 0 0 read/write w w w w w w w w bit addressing 8 8 8 8 1/8 8 8 8 tmod0.7 bit 7 0 always logic zero tmod0.6?.4 timer/counter 0 input clock selection bits 0 0 0 external clock input at tcl0 pin on rising edge 0 0 1 external clock input at tcl0 pin on falling edge 1 0 0 fxx/2 10 ( 4.09 khz ) 1 0 1 fxx/2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx (4.19 mhz) tmod0.3 clear counter and resume counting control bit 1 clear tcnt0, irqt0, and tol0 and resume counting immediately (this bit is cleared automatically when counting starts.) tmod0.2 enable/disable timer/counter 0 bit 0 disable timer/counter 0; retain tcnt0 contents 1 enable timer/counter 0 tmod0.1 bit 1 0 always logic zero tmod0.0 bit 0 0 always logic zero
memory map S3C72K8/p72k8 4 - 38 to e ? timer output enable flag register t/c 0 f 92 h bit 3 2 1 0 identifier "0" toe0 "0" "0" reset reset value 0 0 0 0 read/write r/w r/w r/w r/w bit addressing 1/4 1/4 1/4 1/4 .3 bit 3 0 always logic zero toe0 timer/counter 0 output enable flag 0 disable timer/counter 0 output at the tclo0 pin 1 enable timer/counter 0 output at the tclo0 pin .1?.0 bit 1?0 0 always logic zero
S3C72K8/p72k8 memory map 4 - 39 wdmod ? watch-dog timer mode register f 98 h, f 99 h bit 7 6 5 4 3 2 1 0 identifier .7 .6 .5 .4 .3 .2 .1 .0 reset reset value 1 0 1 0 0 1 0 1 read/write w w w w w w w w bit addressing 8 8 8 8 8 8 8 8 .7 - .0 watch-dog timer enable/disable control 5ah disable watch-dog timer function any other value enable watch-dog timer function wdtcf ? watch-dog timer flag f9a h bit 3 2 1 0 identifier wdtcf ?0? ?0? ?0? reset reset value 0 0 0 0 read/write w ? ? ? bit addressing 1 ? ? ? .3 watch-dog timer's counter clear bit 1 clear and restart the watch-dog timer's counter note : instruction that clear the watch-dog timer (?bit s wdtcf?) should be executed at proper points in a program within a given period. if not executed within a given period and watch-dog timer overflows, reset signal is generated and system is restarted with reset status.
memory map S3C72K8/p72k8 4 - 40 wmod ? watch timer mode register wt f89h, f88h bit 7 6 5 4 3 2 1 0 identifier .7 "0" .5 .4 .3 .2 .1 .0 reset reset value 0 0 0 0 (note) 0 0 0 read/write w w w w r w w w bit addressing 8 8 8 8 1 8 8 8 wmod.7 enable/disable buzzer output bit 0 disable buzzer (buz) signal output at the buz pin 1 enable buzzer (buz) signal output at the buz pin wmod.6 bit 6 0 always logic zero wmod.5?.4 output buzzer frequency selection bits 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 xt in input level control bit 0 input level to xt in pin is low; 1-bit read-only addressable for tests 1 input level to xt in pin is high; 1-bit read-only addressable for tests wmod.2 enable/disable watch timer bit 0 disable watch timer and clear frequency dividing circuits 1 enable watch timer wmod.1 watch timer speed control bit 0 normal speed; set irqw to 0.5 seconds 1 high-speed operation; set irqw to 3.91 ms wmod.0 watch timer clock selection bit 0 select main system clock (fx)/128 as the watch timer clock select main system clock (fx) as a lcd clock source 1 select subsystem clock as the watch timer clock select subsystem clock as the lcd clock source note : reset sets wmod.3 to the current input level of the subsystem clock, xt in . if the input level is high, wmod.3 is set to logic one; if low, wmod.3 is cleared to zero along with all the other bits in the wmod register.
S3C72K8/p72k8 oscillator circuits 6- 1 6 oscillator circuits overview the S3C72K8 microcontroller have two oscillator circuits: a main system clock circuit, and a subsystem clock circuit. the cpu and peripheral hardware operate on the system clock frequency supplied through these circuits. specifically, a clock pulse is required by the following peripheral modules: ? lcd controller ? basic timer ? timer/counter 0 ? watch timer ? serial i/o interface ? clock output circuit cpu clock notation in this document, the following notation is used for descriptions of the cpu clock: fx main - system clock fxt sub - system clock fxx selected system clock clock control registers when the system clock mode register, scmod, and the power control register, pcon, are both cleared to zero after reset , the normal cpu operating mode is enabled, a main system clock is selected as fx/64, and main system clock oscillation is initiated. the pcon is used to select normal cpu operating mode or one of two power down mode-stop or idle. bits 3 and 2 of the pcon register can be manipulated by stop or idle instruction to engage stop or idle power down mode. the scmod, lets you select the main system clock ( fx) or a subsystem clock ( fxt) as the cpu clock and start (or stop) main/sub system clock oscillation. the resulting clock source, either main system clock or subsystem clock, is referred to the selected system clock ( fxx). the main system clock is selected and oscillation started when all scmod bits are cleared to "0". by setting scmod.3, scmod.2 and scmod.0 to different values, you can select a subsystem clock source and start or stop main/sub system clock oscillation. to stop main system clock oscillation, you must use the stop instruction (assuming the main system clock is selected) or manipulate scmod.3 to (assuming the sub system clock is selected). the main system clock frequencies can be divided by 4, 8, or 64 and a subsystem clock frequencies can only be divided by 4. by manipulating pcon bits 1 and 0, you select one of the following frequencies as the cpu clock. fx/4, fxt/4, fx/8, fx/64
oscillator circuits S3C72K8/p72k8 6- 2 using a subsystem clock if a subsystem clock is being used as the selected system clock, the idle power-down mode can be initiated by executing an idle instruction. the watch timer, buzzer and lcd display operate normally with a subsystem clock source, since they operate at very low speed (as low as 122 m s at 32.768 khz) and with very low power consumption. other hardware such as the basic timer, timer/counter 0 and the serial i/o interface should not be driven using the subsystem clock, since they require higher operating speeds for normal performance. x in x out xt in xt out main-system oscillator circuit oscillator stop selector fxx selector sub-system oscillator circuit watch timer scmod.3 scmod.0 fx/1, 2, 16 pcon.1 pcon.2 pcon.3 pcon.0 fxt 1/1-1/4096 frequency dividing circuit 1/2 1/16 basic timer timer/counter0 watch timer lcd controller clock output circuit serial i/o interface wait release signal internal reset signal power down release signal oscillator control circuit pcon.3, .2 clear 1/4 cpu clock fx: main-system clock fxt: sub-system clock fxx: selected system clock cpu stop signal (idle mode) idle stop fx fxt oscillator stop lcd controller figure 6- 1. clock circuit diagram
S3C72K8/p72k8 oscillator circuits 6- 3 main system oscillator circuits x in x out figure 6- 2. crystal/ceramic oscillator ( fx) x in x out external clock figure 6- 3. external oscillator ( fx) x in x out r figure 6- 4. rc oscillator ( fx) subsystem oscillator circuits xt in xt out 32.768 khz figure 6- 5. crystal/ceramic oscillator ( fxt) xt in xt out external clock figure 6- 6. external oscillator ( fxt)
oscillator circuits S3C72K8/p72k8 6- 4 power control register (pcon) the power control register, pcon, is a 4-bit register that is used to select the cpu clock frequency and to con trol cpu operating and power-down modes. pcon can be addressed di rectly by 4-bit write instructions or indirectly by the instructions idle and stop. fb3h pcon.3 pcon.2 pcon.1 pcon.0 pcon bits 3 and 2 are addressed by the stop and idle instructions, respectively, to engage the idle and stop power-down modes. idle and stop modes can be initiated by these instruction despite the current value of the enable memory bank flag (emb). pcon bits 1 and 0 are used to select a specific system clock frequency. there are two basic choices: ? main system clock ( fx) or subsystem clock ( fxt); ? divided fx /4, 8, 64 or fxt /4 clock frequency. pcon.1 and pcon.0 settings are also connected with the system clock mode control register, scmod. if scmod.0 = "0" the main system clock is always selected by the pcon.1 and pcon.0 setting; if scmod.0 = "1" the subsystem clock is selected. reset sets pcon register values (and scmod) to logic zero: scmod.3 and scmod.0 select the main sys tem clock ( fx) and start clock oscillation; pcon.1 and pcon.0 divide the selected fx frequency by 64, and pcon.3 and pcon.2 enable normal cpu operating mode. table 6- 1. power control register (pcon) organization pcon bit settings resulting cpu operating mode pcon.3 pcon.2 0 0 normal cpu operating mode 0 1 idle power-down mode 1 0 stop power-down mode pcon bit settings resulting cpu clock frequency pcon.1 pcon.0 if scmod.0 = "0" if scmod.0 = "1" 0 0 fx/64 fxt/4 1 0 fx/8 1 1 fx/4 + + programming tip ? setting the cpu clock to set the cpu clock to 0.95 m s at 4.19 mhz: bits emb smb 15 ld a,#3h ld pcon,a
S3C72K8/p72k8 oscillator circuits 6- 5 instruction cycle times the unit of time that equals one machine cycle varies depending on whether the main system clock ( fx) or a subsystem clock ( fxt) is used, and on how the oscillator clock signal is divided (by 4, 8, or 64). table 6- 2 shows corresponding cycle times in microseconds. table 6- 2. instruction cycle times for cpu clock rates selected cpu clock resulting frequency oscillation source cycle time ( m m sec) fx/64 65.5 khz fx = 4.19 mhz 15.3 fx/8 524.0 khz 1.91 fx/4 1.05 mhz 0.95 fxt/4 8.19 khz fxt = 32, 768 khz 122.0
oscillator circuits S3C72K8/p72k8 6- 6 system clock mode register (scmod) the system clock mode register, scmod, is a 4-bit register that is used to select the cpu clock and to control main and sub-system clock oscillation. the scmod is mapped to the ram address fb7h. the main clock oscillation is stopped by setting scmod.3 when the clock source is subsystem clock and subsystem clock can be stopped by setting scmod.2 when the clock source is main system clock. scmod.0, scmod.3 cannot be simultaneously modified. the subsystem clock is stopped only by setting scmod.2, and pcon which revokes stop mode cannot stop the subsystem clock. the stop of subsystem clock is released by reset when the selected system clock is main system clock or subsystem clock and is released by setting scmod.2 when the selected system clock is main system clock. reset clears all scmod values to logic zero, selecting the main system clock ( fx) as the cpu clock and starting clock oscillation. the reset value of the scmod is "0". scmod.0, scmod.2, and scmod.3 bits can be manipulated by 1-bit write instructions (in other words, scmod.0, scmod.2, and scmod.3 cannot be modified simultaneously by a 4-bit write). bit 1 is always logic zero. fb7h scmod.3 scmod. 2 "0" scmod.0 a subsystem clock ( fxt) can be selected as the system clock by manipulating the scmod.3 and scmod.0 bit settings. if scmod.3 = "0" and scmod.0 = "1", the subsystem clock is selected and main system clock oscillation continues. if scmod.3 = "1" and scmod.0 = "1", fxt is selected, but main system clock oscillation stops. even if you have selected fx as the cpu clock, setting scmod.3 to "1" will stop main system clock oscillation, and malfunction may be occurred. to operate safely, main system clock should be stopped by a stop instruction is main system clock mode. table 6- 3. system clock mode register (scmod) organization scmod register bit settings resulting clock selection scmod.3 scmod.0 cpu clock fx oscillation 0 0 fx on 0 1 fxt on 1 1 fxt off table 6-4. scmod.2 for sub-oscillation on/off scmod.2 sub-oscillation on/off 0 enable sub system clock 1 disable sub system clock note: you can use scmod.2 as follows (ex; after data bank was used, a few minutes have passed): main operation ? sub-operation ? sub-idle (lcd on, after a few minutes later without any external input) ? sub-operation ? main operation ? scmod.2 = 1 ? main stop mode (lcd off).
S3C72K8/p72k8 oscillator circuits 6- 7 table 6-5. main/sub oscillation stop mode mode condition method to issue osc stop osc stop release source (2) main oscillation stop mode main oscillator runs. sub oscillator runs (stops). system clock is the main oscillation clock. stop instruction: main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). interrupt and reset : after releasing stop mode, main oscillation starts and oscillation stabilization time is elapsed. and then the cpu operates. oscillation stabilization time is 1/[256 x bt clock (fx)] when scmod.3 is set to "1? (1), main oscillator stops, halting the cpu operation. sub oscillator still runs (stops). reset : interrupt can't start the main oscillation. therefore, the cpu operation can never be restarted. main oscillator runs. sub oscillator runs. system clock is the sub oscillation clock. stop instruction (1) : main oscillator stops. cpu is in idle mode. sub oscillator still runs (stops). sub oscillator still runs. bt overflow, interrupt, and reset : after the overflow of basic timer [1/(256 x bt clock (fxt))], cpu operation and main oscillation automatically start. when scmod.3 is set to "1", main oscillator stops. the cpu, however, would still operate. sub oscillator still runs. set scmod.3 to "0" or reset sub oscillation stop mode main oscillator runs. sub oscillator runs. system clock is the main oscillation clock. when scmod.2 to "1", sub oscillator stops, while main oscillator and the cpu would still operate. set scmod.2 to "0" or reset main oscillator runs (stops). sub oscillator runs. system clock is the sub oscillation clock. when scmod.2 to "1", sub oscillator stops, halting the cpu operation. main oscillator still runs (stops). reset notes : 1. this mode must not be used. 2. oscillation stabilization time by interrupt is 1/(2 56 x bt clocks). oscillation stabilization time by a reset is 31.3 ms at 4.19 mhz, main oscillation clock.
oscillator circuits S3C72K8/p72k8 6- 8 switching the cpu clock together, bit settings in the power control register, pcon, and the system clock mode register, scmod, determine whether a main system or a subsystem clock is selected as the cpu clock, and also how this frequency is to be divided. this makes it possible to switch dynamically between main and subsystem clocks and to modify op erating fre quencies. scmod.3, scmod.2, and scmod.0 select the main system clock ( fx) or a subsystem clock ( fxt) and start or stop main system clock oscillation. pcon.1 and pcon.0 control the frequency divider circuit, and divide the selected fx clock by 4, 8, or 64,or fxt clock by 4. note a clock switch operation does not go into effect immediately when you make the scmod and pcon register modifications ? the previously selected clock continues to run for a certain number of machine cycles. for example, you are using the default cpu clock (normal operating mode and a main system clock of fx/64) and you want to switch from the fx clock to a subsystem clock and to stop the main system clock. to do this, you first need to set scmod.0 to "1". this switches the clock from fx to fxt but allows main system clock oscillation to continue. before the switch actually goes into effect, a certain number of machine cycles must elapse. after this time interval, you can then disable main system clock oscillation by setting scmod.3 to "1". this same 'stepped' approach must be taken to switch from a subsystem clock to the main system clock: first, clear scmod.3 to "0" to enable main system clock oscillation. then, after a certain number of machine cycles has elapsed, select the main system clock by clearing all scmod values to logic zero. following a reset , cpu operation starts with the lowest main system clock frequency of 15.3 m s at 4.19 mhz after the standard oscillation stabilization interval of 31.3 ms has elapsed. table 6-4 details the number of machine cycles that must elapse before a cpu clock switch modification goes into effect. table 6-6 . elapsed machine cycles during cpu clock switch after scmod.0 = 0 scmod.0 = 1 before pcon.1 = 0 pcon.0 = 0 pcon.1 = 1 pcon.0 = 0 pcon.1 = 1 pcon.0 = 1 pcon.1 = 0 n/a 1 machine cycle 1 machine cycle n/a pcon.0 = 0 scmod.0 = 0 pcon.1 = 1 8 machine cycles n/a 1 machine cycle n/a pcon.0 = 0 pcon.1 = 1 16 machine cycles 1 machine cycle n/a fx / 4fxt pcon.0 = 1 scmod.0 = 1 n/a n/a 1 machine cycle n/a notes : 1. even if oscillation is stopped by setting scmod.3 during main system clock operation, the stop mode is not entered. 2. since the x in input is connected internally to v ss to avoid current leakage due to the crystal oscillator in stop mode, do not set scmod.3 to "1" or do not use stop instruction when an external clock is used as the main system clock. 3. when the system c lock is switched to the subsystem clock, it is necessary to disable any interrupts which may occur during the time intervals shown in table 6-6. 4. 'n/a' means 'not available'. 5. fx: main-system clock, fxt: sub-system clock. when fx is 4.19 mhz, and fxt is 32.768 khz.
S3C72K8/p72k8 oscillator circuits 6- 9 + + programming tip ? switching between main system and subsystem clock 1. switch from the main system clock to the subsystem clock: ma2sub bits scmod.0 ; s witches to subsystem clock call dly80 ; delay 80 machine cycles bits scmod.3 ; stop the main system clock ret dly80 ld a,#0fh del1 nop nop decs a jr del1 ret 2. switch from the subsystem clock to the main system clock: sub2ma bitr scmod.3 ; start main system clock oscillation call dly80 ; delay 80 machine cycles call dly80 bitr scmod.0 ; switch to main system clock ret
oscillator circuits S3C72K8/p72k8 6- 10 clock output mode register s (clmod) the clock output mode register, clmod, is a 4-bit register that is used to enable or disable clock output to the clo pin and to select the cpu clock source and frequency. clmod is ad dressable by 4-bit write instructions only. fd0h clmod.3 "0" clmod.1 clmod.0 reset clears clmod to logic zero, which automatically selects the cpu clock as the clock source (without initiating clock oscillation), and disables clock output. clmod.3 is the enable/disable clock output control bit; clmod.1 and clmod.0 are used to select one of four possible clock sources and frequencies: normal cpu clock, fxx/8, fxx/16, or fxx/64. table 6-7 . clock output mode register (clmod) organization clmod bit settings resulting clock output clmod.1 clmod.0 clock source frequency 0 0 cpu clock (fx/4, fx/8, fx/64 , fxt/4 ) 1.05 mhz, 524 khz, 65.5 khz , 8.2 khz 0 1 fxx/8 524 khz 1 0 fxx/16 262 khz 1 1 fxx/64 65.5 khz clmod 1 .3 result of clmod 1 .3 setting 0 clock output is disabled (clo1, clo2) 1 clock output is enabled (clo1, clo2) note: frequencies assume that fxx, fx = 4.19 mhz and fxt is 32,768 khz .
S3C72K8/p72k8 oscillator circuits 6- 11 clock output circuit the clock output circuit, used to output clock pulses to the clo pin, has the following components: ? 4-bit clock output mode register (clmod) ? clock selector ? output latch ? port mode flag ? clo output pin (p4.0) clmod.2 clmod.1 clmod.0 clmod.3 4 clock selector p4.0 output latch pm4.0 clo clocks (cpu clock, fxx/8, fxx/16, fxx/64) figure 6- 7. clo output pin circuit diagram clock output procedure the procedure for outputting clock pulses to the clo pin may be summarized as follows: 1. disable clock output by clearing clmod.3 to logic zero. 2. set the clock output frequency (clmod.1, clmod.0). 3. load a "0" to the output latch of the clo pin (p4.0). 4. set the p4.0 mode flag (pm4.0) to output mode. 5. enable clock output by setting clmod.3 to logic one. + + programming tip ? cpu clock output to the clo pin to output the cpu clock to the clo pin: bits emb smb 15 ld ea,# 1 0h ld pmg1,ea ; p 4.0 ? output mode bitr p 4.0 ; clear p 4.0 output latch ld a,#9h ld clmod,a
s3c72k9/p72k8 interrupts 7- 1 7 interrupts overview the S3C72K8 interrupt control circuit has five functional components: ? interrupt enable flags ( iex) ? interrupt request flags ( irqx) ? interrupt master enable register (ime) ? interrupt priority register (ipr) ? power-down release signal circuit three kinds of interrupts are supported: ? internal interrupts generated by on-chip processes ? external interrupts generated by external peripheral devices ? quasi-interrupts used for edge detection and as clock sources table 7- 1. interrupt types and corresponding port pin(s) interrupt type interrupt name corresponding port pins external interrupts int0, int1, int4, intk p1.0, p1.1, p1.3, k0? k3 internal interrupts intb, intt0, ints not applicable quasi-interrupts int2 p1.2 intw not applicable
interrupts s3c72k9/p72k8 7- 2 vectored interrupts interrupt requests may be processed as vectored interrupts in hardware, or they can be generated by program software. a vectored interrupt is generated when the following flags and register settings, corresponding to the specific interrupt ( intn) are set to logic one: ? interrupt enable flag ( iex) ? interrupt master enable flag (ime) ? interrupt request flag ( irqx) ? interrupt status flags (is0, is1) ? interrupt priority register (ipr) if all conditions are satisfied for the execution of a requested service routine, the start address of the interrupt is loaded into the program counter and the program starts executing the service routine from this address. emb and erb flags for ram memory banks and registers are stored in the vector address area of the rom during interrupt service routines. the flags are stored at the beginning of the program with the vent instruction. the initial flag values determine the vectors for resets and interrupts. enable flag values are saved during the main routine, as well as during service routines. any changes that are made to enable flag values during a service routine are not stored in the vector address. when an interrupt occurs, the enable flag values before the interrupt is initiated are saved along with the pro gram status word (psw), and the enable flag values for the interrupt is fetched from the respective vector address. then, if necessary, you can modify the enable flags during the interrupt service routine. when the interrupt service routine is returned to the main routine by the iret instruction, the original values saved in the stack are restored and the main program continues program execution with these values. software-generated interrupts to generate an interrupt request from software, the program manipulates the appropriate irqx flag. when the interrupt request flag value is set, it is retained until all other conditions for the vectored interrupt have been met, and the service routine can be initiated. multiple interrupts by manipulating the two interrupt status flags (is0 and is1), you can control service routine initialization and thereby process multiple interrupts simultaneously. if more than four interrupts are being processed at one time, you can avoid possible loss of working register data by using the push rr instruction to save register contents to the stack before the service routines are exe cuted in the same register bank. when the routines have executed successfully, you can restore the register con tents from the stack to working memory using the pop instruction. power-down mode release an interrupt (with the exception of int0) can be used to release power-down mode (stop or idle). interrupts for power-down mode release are initiated by setting the corresponding interrupt enable flag. even if the ime flag is cleared to zero, power-down mode will be released by an interrupt request signal when the interrupt enable flag has been set. in such cases, the interrupt routine will not be executed since ime = "0".
s3c72k9/p72k8 interrupts 7- 3 no no retain value until ime= 1 retain value until iex = 1 no interrupt is generated (int xx) iex = 1? ime = 1? is1, 0 = 0, 0? is1, 0 = 0, 1? request flag (irqx) 1 generate corresponding vector interrupt and release power-down mode store contents of pc and psw in the stack area; set pc contents to corresponding vector address high-priority interrupt? are both interrupt sources of shared vector address used? is1, 0 = 1, 0 retain value until interrupt service routine is completed no irqx flag value remains 1 jump to interrupt start address verify interrupt source and clear irqx with a btstz instruction reset corresponding irqx flag jump to interrupt start address is1, 0 = 0, 1 yes no yes yes yes yes no yes figure 7- 1. interrupt execution flowchart
interrupts s3c72k9/p72k8 7- 4 note: stop and idle mode can be released by int0. ie2 iew iek iet0 ies ie1 ie0 ie4 ieb intb ime ipr is1 is0 vector interrupt generator @ = edge detection circuit power-down mode release signal interrupt control unit k0-k3 int2 @ imod0 imod1 int4 int0 int1 intw ints intt0 @ @ imodk imod2 @ irqb irq4 irq0 irq1 irqs irqt0 irqk irqw irq2 (note) figure 7- 2. interrupt control circuit diagram
s3c72k9/p72k8 interrupts 7- 5 multiple interrupts the interrupt controller can service multiple interrupts in two ways: as two-level interrupts, where either all inter - rupt requests or only those of highest priority are serviced, or as multi-level interrupts, when the interrupt service routine for a lower-priority request is accepted during the execution of a higher priority routine. two-level interrupt handling two-level interrupt handling is the standard method for processing multiple interrupts. when the is1 and is0 bits of the psw (fb0h.3 and fb0h.2, respectively) are both logic zero, program execution mode is normal and all interrupt requests are serviced (see figure 7- 3). whenever an interrupt request is accepted, is1 and is0 are incremented by one ("0" ? "1" or "1" ? "0"), and the values are stored in the stack along with the other psw bits. after the interrupt routine has been serviced, the modified is1 and is0 values are automatically restored from the stack by an iret instruction. is0 and is1 can be manipulated directly by 1-bit write instructions, regardless of the current value of the enable memory bank flag (emb). before you can modify an interrupt service flag, however, you must first disable interrupt processing with a di instruction. when is1 = "0" and is0 = "1", all interrupt service routines are inhibited except for the highest priority interrupt currently defined by the interrupt priority register (ipr). high level interrupt generated normal program processing (status 0) set ipr int enable int disable high or low level interrupt processing (status 1) high level interrupt processing (status 2) low or high level interrupt generated figure 7- 3. two-level interrupt handling
interrupts s3c72k9/p72k8 7- 6 multi-level interrupt handling with multi-level interrupt handling, a lower-priority interrupt request can be executed while a high-priority inter rupt is being serviced. this is done by manipulating the interrupt status flags, is0 and is1 (see table 7- 2). when an interrupt is requested during normal program execution, interrupt status flags is0 and is1 are set to "1" and "0", respectively. this setting allows only highest-priority interrupts to be serviced. when a high-priority request is accepted, both interrupt status flags are then cleared to "0" by software so that a request of any priority level can be serviced. in this way, the high- and low -priority requests can be serviced in parallel (see figure 7- 4). table 7- 2. is1 and is0 bit manipulation for multi-level interrupt handling process status before int effect of isx bit setting after int ack is1 is0 is1 is0 0 0 0 all interrupt requests are serviced. 0 1 1 0 1 only high-priority interrupts as determined by the current settings in the ipr register are serviced. 1 0 2 1 0 no additional interrupt requests will be serviced. ? ? ? 1 1 value undefined ? ? normal program processing (status 0) low or high level interrupt generated int enable low or high level interrupt generated set ipr int disable int disable modify status int enable high level interrupt generated single interrupt status 0 status 0 3-level interrupt status 2 2-level interrupt status 1 status 1 figure 7- 4. multi-level interrupt handling
s3c72k9/p72k8 interrupts 7- 7 interrupt priority register (ipr) the 4-bit interrupt priority register (ipr) is used to control multi-level interrupt handling. its reset value is logic zero. before the ipr can be modified by 4-bit write instructions, all interrupts must first be disabled by a di instruction. fb2h ime ipr.2 ipr.1 ipr.0 by manipulating the ipr settings, you can choose to process all interrupt requests with the same priority level, or you can select one type of interrupt for high-priority processing. a low-priority interrupt can itself be interrupted by a high-priority interrupt, but not by another low-priority interrupt. a high-priority interrupt cannot be interrupted by any other interrupt source. table 7- 3. standard interrupt priorities interrupt default priority intb, int4 1 int0 2 int1 3 ints 4 intt0 5 intk 6 the msb of the ipr, the interrupt master enable flag (ime), enables and disables all interrupt processing. even if an interrupt request flag and its corresponding enable flag are set, a service routine cannot be executed until the ime flag is set to logic one. the ime flag can be directly manipulated by ei and di instructions, regardless of the current enable memory bank (emb) value. table 7- 4. interrupt priority register settings ipr.2 ipr.1 ipr.0 result of ipr bit setting 0 0 0 process all interrupt requests at low priority (note) 0 0 1 process intb and int4 interrupts only 0 1 0 process int0 interrupts only 0 1 1 process int1 interrupts only 1 0 0 process ints interrupts only 1 0 1 process intt0 interrupts only 1 1 0 process intk interrupts only note : when all interrupts are low priority (the lower three bits of the ipr register are logic zero), the interrupt requested first will have high priority. therefore, the first-request interrupt cannot be superceded by any other interrupt.
interrupts s3c72k9/p72k8 7- 8 + + programming tip ? setting the int interrupt priority the following instruction sequence sets the int1 interrupt to high priority: bits emb smb 15 di ; ipr.3 (ime) ? 0 ld a,#3h ld ipr,a ei ; ipr.3 (ime) ? 1 external interrupt 0, 1 and 2 mode registers (imod0, imod1 and imod2) the following components are used to process external interrupts at the int0, int1 and int2 pins: ? edge detection circuit ? three mode registers, imod0, imod1 and imod2 the mode registers are used to control the triggering edge of the input signal. imod0, imod1 and imod2 settings let you choose either the rising or falling edge of the incoming signal as the interrupt request trigger. the int4 interrupt is an exception since its input signal generates an interrupt request on both rising and falling edges. since int2 is a qu a si-interrupt, the interrupt request flag (irq2) must be cleared by software. fb4h "0" "0" imod0.1 imod0.0 fb5h "0" "0" "0" imod1.0 f da h "0" "0" "0" imod2.0 imod0, imod1 and imod2 are addressable by 4-bit write instructions. reset clears all imod values to logic zero, selecting rising edges as the trigger for incoming interrupt requests. table 7- 5. imod0, 1 and 2 register organization imod0 imod0.3 0 imod0.1 imod0.0 effect of imod0 settings 0 0 rising edge detection 0 1 falling edge detection 1 0 both rising and falling edge detection 1 1 irq0 flag cannot be set to "1" imod1 imod2 0 0 0 imod1.0 imod2.0 effect of imod1 and imod2 settings 0 rising edge detection 1 falling edge detection
s3c72k9/p72k8 interrupts 7- 9 external interrupt 0, 1 , and 2 mode registers (c ontinued ) irq2 imod1 int2 p1.2 p1.0 edge detection irq1 edge detection int1 edge detection irq0 int0 p1.1 imod2 imod0 2 figure 7- 5. circuit diagram for int0, int1 , and int2 pins when modifying the imod registers, it is possible to accidentally set an interrupt request flag. to avoid unwanted interrupts, take these precautions when writing your programs: 1. disable all interrupts with a di instruction. 2. modify the imod register. 3. clear all relevant interrupt request flags. 4. enable the interrupt by setting the appropriate iex flag. 5. enable all interrupts with a n ei instructions.
interrupts s3c72k9/p72k8 7- 10 external key interrupt mode register (imodk) the mode register for external key interrupts at the k0 ?k 3 pins, imodk, is addressable only by 4-bit write instructions. reset clears all imodk bits to logic zero. fb6h "0" imodk.2 imodk.1 imodk.0 rising or falling edge can be detected by bit imodk.2 settings. if a rising or falling edge is detected at any one of the selected k pin by the imodk register, the irqk flag is set to logic one and a release signal for power-down mode is generated. table 7- 6. imodk register bit settings imodk 0 imodk.2 imodk.1 imodk.0 effect of imodk settings 0, 1 0 0 disable key interrupt 0 1 enable edge detection at the k0? k1 pins 1 0 enable edge detection at the k 0 ? k2 pins 1 1 enable edge detection at the k0?k 3 pins imodk.2 0 falling edge detection 1 rising edge detection note s : 1. to generate a key interrupt, the selected pins must be configured to input mode. if any one pin of the selected pins is configured to output mode, only falling edge can be detected. 2 . to generate a key interrupt, first, configure pull-up resistors or external pull-down resistors. and then, select edge detection and pins by setting imodk register.
s3c72k9/p72k8 interrupts 7- 11 p0.3/k3 p0.2/k2 p0.1/k1 p0.0/k0 pin selector imodk rising/ falling edge selector irqk figure 7- 6. circuit diagram for intk + + programming tip ? using intk as a key input interrupt when the key interrupt is used, the selected key interrupt source pin must be set to input: 1. when k0?k 3 are selected ( four pins): bits emb smb 15 ld ea,#00h ld pmg1,ea ; p0 , p4 ? input mode ld ea,#01h ld pumod1,ea ; enable p0 pull-up resistors ld a,#3h ld imodk,a ; (imodk) ? #3h, k0?k3 falling edge select
interrupts s3c72k9/p72k8 7- 12 interrupt flags there are three types of interrupt flags: interrupt request and interrupt enable flags that correspond to each interrupt, the interrupt master enable flag, which enables or disables all interrupt processing. interrupt master enable flag (ime) the interrupt master enable flag, ime, enables or disables all interrupt processing. therefore, even when an irqx flag is set and its corresponding iex flag is enabled, the interrupt service routine is not executed until the ime flag is set to logic one. the ime flag is located in the ipr register (ipr.3). it can be directly be manipulated by ei and di instructions, regardless of the current value of the enable memory bank flag (emb). ime ipr.2 ipr.1 ipr.0 effect of bit settings 0 inhibit all interrupts 1 enable all interrupts interrupt enable flags ( iex) iex flags, when set to logical one, enable specific interrupt requests to be serviced. when the interrupt request flag is set to logical one, an interrupt will not be serviced until its corresponding iex flag is also enabled. interrupt enable flags can be read, written, or tested directly by 1-bit instructions. iex flags can be addressed directly at their specific ram addresses, despite the current value of the enable memory bank (emb) flag. table 7- 7. interrupt enable and interrupt request flag addresses address bit 3 bit 2 bit 1 bit 0 fb8h ie4 irq4 ieb irqb fbah "0" "0" iew irqw fbbh "0" "0" ie k irq k fbch "0" "0" iet0 irqt0 fbdh "0" "0" ies irqs fbeh ie1 irq1 ie0 irq0 fbfh "0" "0" ie2 irq2 notes: 1. iex refers generically to all interrupt enable flags. 2. irqx refers generically to all interrupt request flags. 3. iex = 0 is interrupt disable mode. 4. iex = 1 is interrupt enable mode.
s3c72k9/p72k8 interrupts 7- 13 interrupt request flags ( irqx) interrupt request flags are read/write addressable by 1-bit or 4-bit in structions. irqx flags can be addressed directly at their specific ram addresses, regardless of the current value of the enable memory bank (emb) flag. when a specific irqx flag is set to logic one, the corresponding interrupt request is generated. the flag is then automatically cleared to logic zero when the interrupt has been serviced. exceptions are the watch timer interrupt request flags, irqw, and the external interrupt 2 flag irq2, which must be cleared by software after the interrupt service routine has executed. irqx flags are also used to execute interrupt requests from software. in summary, follow these guidelines for using irqx flags: 1. irqx is set to request an interrupt when an interrupt meets the set condition for interrupt generation. 2. irqx is set to "1" by hardware and then cleared by hardware when the interrupt has been serviced (with the exception of irqw and irq2). 3. when irqx is set to "1" by software, an interrupt is generated. when two interrupts share the same service routine start address, interrupt processing may occur in one of two ways: ? when only one interrupt is enabled, the irqx flag is cleared automatically when the interrupt has been serviced. ? when two interrupts are enabled, the request flag is not automatical ly cleared so that the user has an opportunity to locate the source of the interrupt request. in this case, the irqx setting must be cleared manually using a btstz instruction. table 7- 8. interrupt request flag conditions and priorities interrupt source internal / external pre-condition for irqx flag setting interrupt priority irq flag name intb i reference time interval signal from basic timer 1 irqb int4 e both rising and falling edges detected at int4 1 irq4 int0 e rising or falling edge detected at int0 pin 2 irq0 int1 e rising or falling edge detected at int1 pin 3 irq1 ints i completion signal for serial transmit-and- receive or receive-only operation 4 irqs intt0 i signals for tcnt0 and tref0 registers match 5 irqt0 intk e when a rising or falling edge detected at any one of the k0? k3 pins 6 irqk int2 (note) e rising or falling edge detected at int2 ? irq2 intw i time interval of 0.5 secs or 3.19 msecs ? irqw note: the quasi-interrupt int2 is only used for testing incoming signals.
interrupts s3c72k9/p72k8 7- 14 + + programming tip ? enabling the intb and int4 interrupts to simultaneously enable intb and int4 interrupts: intb di btstz irqb ; irqb = 1 ? jr int4 ; if no, int4 interrupt; if yes, intb interrupt is processed ? ? ? ei iret ; int4 bitr irq4 ; int4 is processed ? ? ? ei iret
s3c72k9/p72k8 power-down 8- 1 8 power-down overview the S3C72K8 microcontroller has two power-down modes to reduce power consumption: idle and stop. idle mode is initiated by the idle instruction and stop mode by the instruction stop. (several nop instructions must always follow an idle or stop instruction in a program.) in idle mode, the cpu clock stops while pe ripherals and the oscillation source continue to operate normally. when reset occurs during normal operation or during a power-down mode, a reset operation is initiated and the cpu enters idle mode. when the standard oscillation stabilization time interval (31.3 ms at 4.19 mhz) has elapsed, normal cpu operation resumes. in stop mode, main system clock oscillation is halted (assuming it is currently operating), and peripheral hard - ware components are powered-down. the effect of stop mode on specific peripheral hardware components ? cpu, basic timer, ser ial i/o, timer/ counters 0 , watch timer, and lcd controller ? and on external interrupt requests, is detailed in table 8- 1. note do not use stop mode if you are using an external clock source because x in input must be restricted internally to v ss to reduce current leakage. idle or stop modes are terminated either by a reset , or by an interrupt which is enabled by the corresponding interrupt enable flag, iex. when power-down mode is terminated by reset , a normal reset operation is executed. assuming that both the interrupt enable flag and the interrupt request flag are set to "1", power-down mode is released immediately upon entering power-down mode. when an interrupt is used to release power-down mode, the operation differs depending on the value of the interrupt master enable flag (ime): ? if the ime flag = "0", program execution start s immediately after the instruction which issues the request to enter power-down mode is executed. the interrupt request flag remains set to logical one. ? if the ime flag = "1", two instructions are executed after the power-down mode release and the vectored interrupt is then initiated. however, when the release signal is caused by int2 or intw, the operation is identical to the ime = "0" condition. assuming that both interrupt enable flag and interrupt request flag are set to "1", the release signal is generated when power-down mode is entered.
power-down s3c72k9/p72k8 8- 2 table 8- 1. hardware operation during power-down modes operation stop mode (stop) idle mode (idle) system clock status can be changed only if the main system clock is used can be changed if the main system clock or subsystem clock is used clock oscillator main system clock oscillation stops cpu clock oscillation stops (main and subsystem clock oscillation continues) basic timer basic timer stops basic timer operates (with irqb set at each reference interval) serial i/o interface operates only if external sck input is selected as the serial i/o clock operates if a clock other than the cpu clock is selected as the serial i/o clock timer/counter 0 operates only if tcl0 is selected as the counter clock timer/counter 0 operates watch timer operates only if subsystem clock (fxt) is selected as the counter clock watch timer operates lcd controller operates only if a subsystem clock is se - lected as lcdck lcd controller operates external interrupts int1, int2, int4, and intk are acknowledged ; int0 is not serviced int0, int1, int2, int4, and intk are acknowledged (note) cpu all cpu operations are disabled all cpu operations are disabled mode release signal interrupt request signals (except int0) are enabled by an interrupt enable flag or by reset input interrupt request signals are enabled by an interrupt enable flag or by reset input (note) note: int0 can be operated in idle mode only when fxx/64 is selected as a sampling clock. table 8-2. system operating mode comparison mode condition stop/idle mode start method current consumption main operating mode main oscillator runs sub oscillator runs system clock is the main oscillation clock ? a main idle mode main oscillator runs sub oscillator runs system clock is the main oscillation clock idle instruction b main stop mode main oscillator runs sub oscillator runs system clock is the main oscillation clock stop instruction d sub operating mode main oscillator is stopped by scmod.3. sub oscillator runs system clock is the sub oscillation clock ? c sub idle mode main oscillator is stopped by scmod.3. sub oscillator runs system clock is the sub oscillation clock idle instruction d note: the current consumption is: a > b > c > d
s3c72k9/p72k8 power-down 8- 3 idle mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset idle instruction normal mode idle mode normal mode clock signal normal oscillation figure 8- 1. timing when idle mode is released by reset reset clock signal normal oscillation mode release signal idle instruction interrupt acknowledge (ime = 1) normal mode idle mode normal mode figure 8- 2. timing when idle mode is released by an interrupt
power-down s3c72k9/p72k8 8- 4 stop mode timing diagrams oscillator stabilization wait time (31.3 ms/4.19 mhz) reset stop instruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes figure 8- 3. timing when stop mode is released by reset reset oscillator stabilization wait time (bmod setting) stop instruction normal mode normal mode clock signal stop mode idle mode oscillation stops oscillation resumes mode release signal int ack (ime=1) figure 8- 4. timing when stop mode is release by an interrupt
s3c72k9/p72k8 power-down 8- 5 + + programming tip ? reducing power consumption for key input interrupt processing the following code shows real-time clock and interrupt processing for key inputs to reduce power consumption. in this example, the system clock source is switched from the main system clock to a subsystem clock and the lcd display is turned on: keyclk di call ma2sub ; main system clock ? subsystem clock switch subroutine smb 15 ld ea,#00h ld p2 ,ea ; all key strobe outputs to low level ld a,#3h ld imodk,a ; select k0 ? k3 enable smb 0 bitr irqw bitr irqk bits iew bits iek clks1 call watdis ; execute clock and display changing subroutine btstz irqk jr cidle call sub2ma ; subsystem clock ? main system clock switch subroutine ei ret cidle idle ; engage idle mode nop nop nop jps clks1
power-down s3c72k9/p72k8 8- 6 recommended connections for unused pins to reduce overall power consumption, please configure unused pins according to the guidelines described in table 8-3 . table 8-3 . unused pin connections for reduced power consumption pin/share pin names recommended connection p0.0/ sck /k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 input mode: connect to v dd output mode: no connection p1.0/cin0/int0 p1.1/cin1/int1 p1.2/int2 p1.3/int4 connect to v dd (1) p 2.0?p2.3 input mode: connect to v dd output mode: no connection p 3.0?p3.1 p3.2/lcdsy p3.0/lcdck p4.0/clo p4.1/tcl0 p4.2/tclo0 input mode: connect to v dd output mode: no connection p5.0/seg32?p5.7/seg39 no connection (2) seg0?seg29 seg30?seg31 com0?com7 no connection v lc1 ?v lc5 no connection xt in connect xt in to v ss or v dd xt out no connection test connect to v ss notes: 1. digital mode at p1.0?p1.1. 2. used as segment.
S3C72K8/p72k8 reset reset 9- 1 9 reset reset overview when a reset signal is input during normal operation or power-down mode, a hardware reset operation is initiated and the cpu enters idle mode. then, when the standard oscillation stabilization interval of 31.3 ms at 4.19 mhz has elapsed, normal system operation resumes. regardless of when the reset occurs ? during normal operating mode or during a power-down mode ? most hardware register values are set to the reset values described in table 9- 1 below. the current status of several register values is, however, always retained when a reset occurs during idle or stop mode; if a reset occurs during normal operating mode, their values are undefined. current values that are retained in this case are as follows: ? carry flag ? data memory values ? general-purpose registers e, a, l, h, x, w, z, and y ? serial i/o buffer register (sbuf) oscillator stabilization wait time (31.3 ms/4.19 mhz) operatng mode idle mode normal mode or power-down mode reset input reset operation figure 9- 1. timing for oscillation stabilization after reset reset
reset reset S3C72K8/p72k8 9- 2 hardware re gister values after reset reset table 9- 1 gives you detailed information about hardware register values after a reset occurs during power- down mode or during normal operation. table 9- 1. hardware register values after reset reset hardware component or sub component if reset reset occurs during power-down mode if reset reset occurs during normal operation program counter (pc) lower six bits of address 0000h are transferred to pc1 1? 8, and the contents of 0001h to pc7 ? 0. lower six bits of address 0000h are transferred to pc1 1 ?8, and the contents of 0001h to pc7?0. bank selection registers (smb, srb) 0, 0 0, 0 bsc register (bsc0?bsc3) 0 0 program status word (psw): carry flag (c) retained undefined skip flag (sc0?sc2) 0 0 interrupt status flags (is0, is1) 0 0 bank enable flags (emb, erb) bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. bit 6 of address 0000h in program memory is transferred to the erb flag, and bit 7 of the address to the emb flag. stack pointer (sp) undefined undefined data memory (ram): general registers e, a, l, h, x, w, z, y values retained undefined general purpose registers values retained undefined clocks: power control register (pcon) 0 0 clock output mode register (clmod) 0 0 system clock mode register (scmod) 0 0 interrupts: interrupt request flags (irqx) 0 0 interrupt enable flags (iex) 0 0 interrupt priority flag (ipr) 0 0 interrupt master enable flag (ime) 0 0 int0 mode register (imod0) 0 0 int1 mode register (imod1) 0 0 int2 mode register (imod2) 0 0 intk mode register (imodk) 0 0
S3C72K8/p72k8 reset reset 9- 3 table 9- 1. hardware register values after reset (continued) hardware component or sub component if reset reset occurs during power-down mode if reset reset occurs during normal operation i/o ports: output buffers off off output latches 0 0 port mode flags (pm) 0 0 pull-up resistor mode reg (pumod1/2) 0 0 basic timer: count register (bcnt) undefined undefined mode register (bmod) 0 0 watchdog mode register ( wd mod) a5h a5h watchdog counter clear flag (wdtcf) 0 0 timer/counters 0: count registers (tcnt0) 0 0 reference registers (tref0) ffh ffh mode registers (tmod0) 0 0 output enable flags (toe0) 0 0 watch timer: watch timer mode register (wmod) 0 0 lcd driver/controller: lcd mode register (lmod) 0 0 lcd control register (lcon) 0 0 display data memory values retained undefined output buffers off off serial i/o interface: sio mode register (smod) 0 0 sio interface buffer (sbuf) values retained undefined n-channel open-drain mode register pne 1/2/3 0 0 comparator comparator mode register (cmod) 0 0 comparison result register undefined undefined
S3C72K8/p72k8 i/o ports 10- 1 10 i/o ports overview the S3C72K8 has 6 ports. there are total of 4 input pins, 8 output pins (sharing with segment driver output) and 15 configurable i/o pins, for a maximum number of 27 pins. pin addresses for all ports are mapped to bank 15 of the ram. the contents of i/o port pin latches can be read, written, or tested at the corresponding address using bit manipulation instructions. port mode flags port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. port 1 mode register (p1mod) port 1 (p1.0?p1.1) can be used for either digital or analog input. p1mod register settings determine the input mode (digital or analog) for specific port 1 pins. pull- u p resistor mode register (pumod) the pull-up mode registers (pumod1, 2) are used to assign internal pull-up resistors by software to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. n-channel open-drain mode register (pne) the n-channel open-drain mode register (pne) is used to configure outputs as n-channel, open-drain outputs or as push-pull outputs.
i/o ports S3C72K8/p72k8 10- 2 table 10- 1. i/o port overview port i/o pins pin names address function description 0 i/o 4 p0.0?p0.3 ff0h 4-bit i/o port. 1-bit and 4-bit read/write and test is possible. individual pins are software configurable as input or output. individual pins are software configurable as open-drain or push-pull output. 4-bit pull-up resistors are software assignable; pull-up resistors are automatically disabled for output pins. 1 i 4 p1.0?p1.3 ff1h 4-bit input port. 1-bit and 4-bit read and test is possible. the 1-bit unit pull-up resistors are assigned to input pins by software. an interrupt is generated by digital input at p1.0, p1.1. 2 i/o 4 p2.0?p2. 3 ff2h same as port 0 except that 8-bit read/write and test possible. 3 i/o 4 p3.0?p3.3 ff3h 4 i/o 3 p 4 .0?p 4 . 2 ff 4 h same as port 0 except that port 4 is 3-bit i/o port and configurabled as analog input pin. 5 i/o 8 p5.0?p5.7 1fxh.0 (note) output port for 1-bit data note: "x" means an even-numbered value from "0h" to "fh". table 10- 2. port pin status during instruction execution instruction type example input mode status output mode status 1-bit test 1-bit input 4-bit input 8-bit input btst ldb ld ld p0.1 c,p1.3 a,p0 ea,p 4 input or test data at each pin input or test data at output latch 1-bit output bitr p2.3 output latch contents undefined output pin status is modified 4-bit output 8-bit output ld ld p2,a p6,ea transfer accumulator data to the output latch transfer accumulator data to the output pin
S3C72K8/p72k8 i/o ports 10- 3 port mode flags (pm flags) port mode flags (pm) are used to configure i/o ports to input or output mode by setting or clearing the corresponding i/o buffer. for convenient program reference, pm flags are organized into six groups ? pmg1 and pmg2 as shown in table 10- 3. they are ad dressable by 8-bit write instructions only. when a pm flag is "0", the port is set to input mode; when it is "1", the port is enabled for output. reset clears all port mode flags to logical zero, automatically configuring the corresponding i/o ports to input mode. table 10- 3. port mode group flags pm group id address bit 3 bit 2 bit 1 bit 0 pmg1 fe 6 h pm0.3 pm0.2 pm0.1 pm0.0 fe 7 h "0" pm 4 .2 pm 4 .1 pm 4 .0 pmg2 fe 8 h pm 2 .3 pm 2 .2 pm 2 .1 pm 2 .0 fe 9 h pm3.3 pm3.2 pm3.1 pm3.0 note: if bit = "0", the corresponding i/o pin is set to input mode. if bit = "1", the pin is set to output mode: pm0.0 for p0.0, pm0.1 for p0.1, etc , . all flags are cleared to "0" following reset . + + programming tip ? configuring i/o ports to input or output configure ports 0 and 2 as an output port: bits emb smb 15 ld ea,# 7 fh ld pmg1,ea ; p0 and p 4 ? output port 1 mode register (p1mod) p1mod register settings determine if port 1 is used for digital input or for analog input. the p1mod register is a 4-bit write only register. p1mod is mapped to address fe2h. a reset operation initializes all p1mod values to logic zero, configuring port 1 as a analog input port. when a p1mod bit is "0", the corresponding pin is configured as a analog input pin. when set to "1", it is configured as an digital input pin: p1mod.0 corresponds to p1.0, and p1mod.1 to p1.1. fe2h "0" "0" p1mod.1 p1mod.0 p1mod note int0 and int1 can occur only when the port is configured to digital input. if you change the input mode from digital to analog using p1mod settings, irq0 and irq1 will be set. when use analog input, you must clear the corresponding interrupt enable flag ( iex). that is, clear ie0 when p1.0 is an analog input and clear ie1 when p1.1 is an analog input.
i/o ports S3C72K8/p72k8 10- 4 pull-up resistor mode register (pumod) the pull-up resistor mode registers (pumod1 and pumod2) are used to assign internal pull-up resistors by software to specific ports. when a configurable i/o port pin is used as an output pin, its assigned pull-up resistor is automatically disabled, even though the pin's pull-up is enabled by a corresponding pumod bit setting. pumod1 is addressable by 8- bit write instructions only , and pumod2 by 4-bit write instruction only . reset clears pumod register values to logic zero, automatically disconnecting all software- assignable port pull-up resis tors. table 10- 4. pull-up resistor mode register (pumod) organization pumod id address bit 3 bit 2 bit 1 bit 0 pumod1 fdch pur3 pur2 "0" pur0 fddh 0 0 0 pur4 pumod2 fdeh pur 1.3 pur 1.2 pur1.1 pur1.0 note: when bit = "1", a pull-up resistor is assigned to the corresponding i/o port: pur3 for port 3, pur2 for port 2, and so on. + + programming tip ? enabling and disabling i/o port pull-up resistors p6 and p7 enable pull-up resistors. bits emb smb 15 ld ea,#0ch ld pumod1,ea ; p 2 and p 3 enable n-channel open-drain mode register (pne) the n-channel open-drain mode register (pne) is used to configure ports 0, 2 , 3 and 4 to n-channel, open-drain or as push-pull outputs. when a bit in the pne register is set to "1", the corresponding output pin is configured to n-channel, open-drain; when set to "0", the output pin is configured to push-pull. the all pne register s consist of an 8-bit register and a 4-bit register; pne1 and pne3 can be addressed by 4-bit write instruction only and pne2 by 8-bit write instructions only. fa6h p0.3 p0.2 p0.1 p0.0 pne1 fa8h p2.3 p2.2 p2.1 p2.0 pne2 fa9h p3.3 p3.2 p3.1 p3.0 faah "0" p4.2 p4.1 p4.0 pne3
S3C72K8/p72k8 i/o ports 10- 5 port 0 circuit diagram cmos push-pull, n-channel open-drain output latch mux 1, 4 1, 4 p0.0/ sck/ k0 p0.1/so/k1 p0.2/si/k2 p0.3/buz/k3 v dd pur0 pm0.0 pm0.1 pm0.2 pm0.3 pm0.0 pm0.1 pm0.2 pm0.3 pne1.0 pne1.1 pne1.2 pne1.3 when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings in the pull-up resistor mode register (pumod). note: figure 10- 1. port 0 circuit diagram
i/o ports S3C72K8/p72k8 10- 6 port 1 circuit diagram v dd p1.0/int0/cin0 p1.1/int1/cin1 p1.2/int2 p1.3/int4 int0 int4 int1 int2 pur1.2 pur1.3 pur1.1 pur1.0 n/r circuit imod digital input analog input external reference digital input analog input digital input digital input n/r = noise reduction figure 10- 2. port 1 circuit diagram
S3C72K8/p72k8 i/o ports 10- 7 port 2 and 3 circuit diagram mux v dd x = 2, 3 b = 0, 1, 2, 3 px.b p-ch purx purx pmx.b output latch pmx.b 1, 4, 8 1, 4, 8 note: when a port pin serves as an output, its pull-up resistor is automatically disable, even though the port's pull-up resistor is enable by bit settings to the pull-up resistor mode register (pumod). figure 10-3. port 2 and 3 circuit diagram
i/o ports S3C72K8/p72k8 10- 8 port 4 circuit diagram cmos push-pull, n-channel open-drain output latch mux p4.0/clo p4.1/tcl0 p4.2/tclo0 pur4 pm4.0 pm4.1 pm4.2 pne3.0 pne3.1 pne3.2 1, 4 v dd 1, 4 pm4.0 pm4.1 pm4.2 note: when a port pin serves as an output, its pull-up resistor is automatically disabled, even though the port's pull-up resistor is enabled by bit settings to the pull-up resistor mode register (pumod). figure 10-4 . port 4 circuit diagram
S3C72K8/p72k8 timers and timer/counters 11- 1 11 timers and timer/counters overview the S3C72K8 microcontroller has four timer and timer/counter modules: ? 8-bit basic timer (bt) ? 8-bit timer/counter (tc0) ? watch timer (wt) the 8-bit basic timer (bt) is the microcontroller's main interval timer and watchdog timer . it generates an interrupt request at a fixed time interval when the appropriate modification is made to its mode register. the basic timer is also used to determine clock oscillation stabilization time when stop mode is released by an interrupt and after a reset . the 8-bit timer/counter (tc0) is programmable timer/counter that is used primarily for event counting and for clock frequency modification and output. in addition, tc 0 generates a clock signal that can be used by the serial i/o interface. the watch timer (wt) module consists of an 8-bit watch timer mode register, a clock selector, and a frequency divider circuit. watch timer functions include real-time and watch-time measurement, main and subsystem clock interval timing, buzzer output generation. it also generates a clock signal for the lcd controller.
timers and t imer/counters S3C72K8/p72k8 11- 2 basic timer (bt) overview the 8-bit basic timer (bt) has five functional components: ? clock selector logic ? 4-bit mode register (bmod) ? 8-bit counter register (bcnt) ? 8-bit watchdog timer mode register (wdmod) ? watchdog timer counter clear flag (wdtcf) the basic timer generates interrupt requests at precise intervals, based on the frequency of the system clock. you can use the basic timer as a "watchdog" timer for monitoring system events or use bt output to stabilize clock oscillation when stop mode is released by an interrupt and following reset . bit settings in the basic timer mode register bmod turns the bt module on and off, selects the input clock frequency, and controls interrupt or stabilization intervals. interval timer function the basic timer's primary function is to measure elapsed time intervals. the standard time interval is equal to 256 basic timer clock pulses. to restart the basic timer, one bit setting is required: bit 3 of the mode register bmod should be set to logic one. the input clock frequency and the interrupt and stabilization interval are selected by loading the appropriate bit values to bmod.2-bmod.0. the 8-bit counter register, bcnt, is incremented each time a clock signal is detected that corresponds to the frequency selected by bmod. bcnt continues incrementing as it counts bt clocks until an overflow occurs ( 3 255). an overflow causes the bt interrupt request flag (irqb) to be set to logic one to signal that the designated time interval has elapsed. an interrupt request is than generated, bcnt is cleared to logic zero, and counting continues from 00h. watchdog timer function the basic timer can also be used as a "watchdog" timer to signal the occurrence of system or program operation error. for this purpose, instruction that clear the watchdog timer (bits wdtcf) should be executed at proper points in a program within given period. if an instruction that clears the watchdog timer is not executed within the given period and the watchdog timer overflows, reset signal is generated and the system restarts with reset status. an operation of watchdog timer is as follows: ? write some values (except #5ah) to watchdog timer mode register, wdmod. ? if wdcnt overflows, system reset is generated.
S3C72K8/p72k8 timers and timer/counters 11- 3 oscillation stabilization interval control bits 2?0 of the bmod register are used to select the input clock frequency for the basic timer. this setting also determines the time interval (also referred to as 'wait time') required to stabilize clock signal oscillation when stop mode is released by an interrupt. when a reset signal is inputted, the standard stabilization interval for system clock oscillation following the reset is 31.3 ms at 4.19 mhz. table 11-1. basic timer register overview register name type description size ram address addressing mode reset value bmod control controls the clock frequency (mode) of the basic timer; also, the oscillation stabilization interval after stop mode release or reset 4-bit f85h 4-bit write-only; bmod.3: 1-bit writeable "0" bcnt counter counts clock pulses matching the bmod frequency setting 8-bit f86h-f87h 8-bit read-only u (note) wdmod control controls watchdog timer operation. 8-bit f98h-f99h 8-bit write-only a5h wdtcf control clears the watchdog timer's counter. 1-bit f9ah.3 1-, 4-bit write ?0? note: 'u' means the value is undetermined after a reset .
timers and t imer/counters S3C72K8/p72k8 11- 4 notes: 1. wait means stabilization time after reset or stabilization time after stop mode release. 2. the reset signal can be generated if the wdmod is toggled for 8 times where "toggle" means change from 5ah to other value and vice verse. 3. when the watdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to "0", the bcnt value is not cleared but increased continuously. as a result, the 3-bit counter of the watchdog timer (wdcnt) can be increased by 1. for example, when the bmod value is x000b and the watchdog timer is enabled, the watchdog timer interval time is from 2 3 x 2 12 x 2 8 /fxx to (2 3 - 1) x 2 12 x 2 8 /fxx. bmod.3 bmod.2 bmod.1 bmod.0 bits instruction overflow clear bcnt "clear" signal 1 pulse period = bt input clock 2 8 (1/2 duty) interrupt request clear irqb cpu clock start signal (power-down release) wait (note) 3-bit counter clear overflow reset bits instruction reset wdtcf clock selector wdcnt wdmod reset signal generation delay clear stop 8 8 bcnt irqb 1-bit r/w clock input 4 figure 11-1. basic timer circuit diagram
S3C72K8/p72k8 timers and timer/counters 11- 5 basic timer mode register (bmod) the basic timer mode register, bmod, is a 4-bit write-only register. bit 3, the basic timer start control bit, is also 1-bit addressable. all bmod values are set to logic zero following reset and interrupt request signal generation is set to the longest interval. (bt counter operation cannot be stopped.) bmod settings have the following effects: ? restart the basic timer; ? control the frequency of clock signal input to the basic timer; ? determine time interval required for clock oscillation to stabilize following the release of stop mode by an interrupt. by loading different values into the bmod register, you can dynamically modify the basic timer clock frequency during program execution. four bt frequencies, ranging from fxx/2 12 to fxx/2 5 , are selectable. since bmod's reset value is logic zero, the default clock frequency setting is fxx/2 12 . the most significant bit of the bmod register, bmod.3, is used to restart the basic timer. when bmod.3 is set to logic one ( ebable) by a 1-bit write instruction, the contents of the bt counter register (bcnt) and the bt interrupt request flag (irqb) are both cleared to logic zero, and timer operation restarts. the combination of bit settings in the remaining three registers ? bmod.2, bmod.1, and bmod.0 ? determine the clock input frequency and oscillation stabilization interval. table 11-2. basic timer mode register (bmod) organization bmod.3 basic timer start control bit 1 start basic timer; clear irqb, bcnt, and bmod.3 to "0" bmod.2 bmod.1 bmod.0 basic timer input clock interrupt interval time (wait time when stop mode is released) 0 0 0 fxx/2 12 (1.02 khz) 2 20 /fxx (250 ms) 0 1 1 fxx/2 9 (8.18 khz) 2 17 /fxx (31.3 ms) 1 0 1 fxx/2 7 (32.7 khz) 2 15 /fxx (7.82 ms) 1 1 1 fxx/2 5 (131 khz) 2 13 /fxx (1.95 ms) notes: 1. clock frequencies and oscillation stabilization assume a system oscillator clock frequency ( fxx) of 4.19 mhz. 2. fxx = system clock frequency. 3. oscillatio n stabilization time is the time required to stabilize clock signal oscillation after stop mode is released. the data in the table column 'oscillation stabilization' can also be interpreted as "interrupt interval time". 4. the standard stabilization time for system clock oscillation following a reset is 31.3 ms at 4.19 mhz.
timers and t imer/counters S3C72K8/p72k8 11- 6 basic timer counter (bcnt) bcnt is an 8-bit counter for the basic timer. it can be addressed by 8-bit read instructions. reset leaves the bcnt counter value undetermined. bcnt is automatically cleared to logic zero whenever the bmod register control bit (bmod.3) is set to "1" to restart the basic timer. it is incremented each time a clock pulse of the frequency determined by the current bmod bit settings is detected. when bcnt has incrementing to hexadecimal 'ffh' ( 3 255 clock pulses), it is cleared to '00h' and an overflow is generated. the overflow causes the interrupt request flag, irqb, to be set to logic one. when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. note always execute a bcnt read operation twice to eliminate the possibility of reading unstable data while the counter is incrementing. if, after two consecutive reads, the bcnt values match, you can select the latter value as valid data. until the results of the consecutive reads match, however, the read operation must be repeated until the validation condition is met. basic timer operation sequence the basic timer's sequence of operations may be summarized as follows: 1. set bmod.3 to logic one to restart the basic timer 2. bcnt is then incremented by one after each clock pulse corresponding to bmod selection 3. bcnt overflows if bcnt = 255 (bcnt = ffh) 4. when an overflow occurs, the irqb flag is set by hardware to logic one 5. the interrupt request is generated 6. bcnt is then cleared by hardware to logic zero 7. basic timer resumes counting clock pulses
S3C72K8/p72k8 timers and timer/counters 11- 7 + + programming tip ? using the basic timer 1. to read the basic timer count register (bcnt): bits emb smb 15 bcntr ld ea,bcnt ld yz,ea ld ea,bcnt cpse ea,yz jr bcntr 2. when stop mode is released by an interrupt, set the oscillation stabilization interval to 31.3 ms: bits emb smb 15 ld a,#0bh ld bmod,a ; wait time is 31.3 ms stop ; set stop power-down mode nop nop nop cpu operation stop instruction stop mode is released by interrupt stop mode idle mode (31.3 ms) normal mode normal mode 3. to set the basic timer interrupt interval time to 1.95 ms (at 4.19 mhz): bits emb smb 15 ld a,#0fh ld bmod,a ei bits ieb ; basic timer interrupt enable flag is set to "1" 4. clear bcnt and the irqb flag and restart the basic timer: bits emb smb 15 bits bmod.3
timers and t imer/counters S3C72K8/p72k8 11- 8 watchdog timer mode register (wdmod) the watchdog timer mode register, wdmod, is a 8-bit write-only register. wdmod register controls to enable or disable the watchdog function. wdmod values are set to logic "a5h" following reset and this value enables the watchdog timer. watchdog timer is set to the longest interval because bt overflow signal is generated with the longest interval. wdmod watchdog timer enable/disable control 5ah disable watchdog timer function any other value enable watchdog timer function watchdog timer counter (wdcnt) the watchdog timer counter, wdcnt, is a 3-bit counter. wdcnt is automatically cleared to logic zero, and restarts whenever the wdtcf register control bit is set to "1". reset, stop, and wait signal clears the wdcnt to logic zero also. wdcnt increments each time a clock pulse of the overflow frequency determined by the current bmod bit setting is generated. when wdcnt has incremented to hexadecimal '07h', it is cleared to ?00h? and an overflow is generated. the overflow causes the system reset . when the interrupt request is generated, bcnt immediately resumes counting incoming clock signals. watchdog timer counter clear flag (wdtcf) the watchdog timer counter clear flag, wdtcf, is a 1-bit write instruction. when wdtcf is set to one, it clears the wdcnt to zero and restarts the wdcnt. wdtcf register bits 2-0 are always logic zero. table 11 - 3. watchdog timer interval time bmod bt input clock wdt interval time (3) x000b fxx/2 12 2 3 2 12 2 8 /fxx - (2 3 -1) 2 12 2 8 /fxx 1.75?2.0 sec x011b fxx/2 9 2 3 2 9 2 8 /fxx - (2 3 -1) 2 9 2 8 /fxx 218.7?250 ms x101b fxx/2 7 2 3 2 7 2 8 /fxx - (2 3 -1) 2 7 2 8 /fxx 54.6?62.5ms x111b fxx/2 5 2 3 2 5 2 8 /fxx - (2 3 -1) 2 5 2 8 /fxx 13.6?15.6 ms notes: 1. clock frequencies assume a system oscillator clock frequency ( fx) of 4.19 mhz 2. fxx = system clock frequency. 3. when the wa tchdog timer is enabled or the 3-bit counter of the watchdog timer is cleared to "0", the bcnt value is not cleared but increased continuously. as a result, the 3-bit counter of the watchdog timer (wdcnt) can be increased by 1. for example, when the bmod value is x000b and the watchdog timer is enabled, the watchdog timer interval time is from 2 3 2 12 2 8 / fxx to (2 3 ?1) 2 12 2 8 / fxx.
S3C72K8/p72k8 timers and timer/counters 11- 9 + + programming tip ? using the watchdog timer reset di ld ea,#00h ld sp,ea ld a,#0dh ; wdcnt input clock is 7.82 ms ld bmod,a main bits wdtcf ; main routine operation period must be shorter than ; watchdog-timer's period jp main
timers and t imer/counters S3C72K8/p72k8 11- 10 8-bit timer/counter 0 (tc0) overview timer/counter 0 (tc0) is used to count system 'events' by identifying the transition (high-to-low or low-to-high) of incoming square wave signals. to indicate that an event has occurred, or that a specified time interval has elapsed, tc0 generates an interrupt request. by counting signal transitions and comparing the current counter value with the reference register value, tc0 can be used to measure specific time intervals. tc0 has a reloadable counter that consists of two parts: an 8-bit reference register (tref0) into which you write the counter reference value, and an 8-bit counter register (tcnt0) whose value is automatically incremented by counter logic. an 8-bit mode register, tmod0, is used to activate the timer/counter and to select the basic clock frequency to be used for timer/counter operations. to dynamically modify the basic frequency, new values can be loaded into the tmod0 register during program execution. timer/counter 0 can supply a clock signal to the clock selector circuit of the serial i/o interface for data shifter and clock counter operations. (these internal sio operations are controlled in turn by the sio mode register, smod). this clock generation function enables you to adjust data transmission rates across the serial interface. tc0 function summary 8-bit programmable timer generates interrupts at specific time intervals based on the selected clock frequency. external event counter counts various system " events " based on edge detect ion of external clock sig nals at the tc0 input pin, tcl0. to start the event counting operation, tmod0.2 is set to " 1 " and tmod0.6 is cleared to " 0 " . arbitrary frequency output outputs selectable clock frequencies to the tc0 output pin, tclo0. external signal divider divides the frequency of an incoming external c lock signal according to a modi fiable reference value (tref0), and outputs the modified frequency to the tclo0 pin. serial i/o clock source outputs a modifiable clock signal for use as the sck clock source.
S3C72K8/p72k8 timers and timer/counters 11- 11 tc0 component summary mode register (tmod0) activates the timer/counter and selects the internal clock frequency or the external clock source at the tcl0 pin. reference register (tref0) stores the reference value for the desired number of clock pulses between interrupt requests. counter register (tcnt0) counts internal or external clock pulses based on the bit settings in tmod0 and tref0. clock selector circuit together with the mode register (tmod0), lets you select one of four internal clock frequencies or an external clock. 8-bit comparator determines when to generate an interrupt by comparing the current value of the counter register (tcnt0) with the reference value previously programmed into the reference register (tref0). output latch (tol0) where a clock pulse is stored pending output to the i/o circuit or to the tc0 output pin, tclo0. when the contents of the tcnt0 and tref0 registers coincide, the timer/counter interrupt request flag (irqt0) is set to "1", the status of tol0 is in verted, and an interrupt is generated. output enable flag (toe0) must be set to logic one before the contents of the tol0 latch can be output to tclo0. interrupt request flag (irqt0) cleared when tc0 operation starts and the tc0 interrupt service routine is executed and set to 1 whenever the counter value and reference value coincide. interrupt enable flag (iet0) must be set to logic one before the interrupt requests generated by timer/counter 0 can be processed. table 11-4 . tc0 register overview register name type description size ram address addressing mode reset value tmod0 control controls tc0 enable/disable (bit 2); clears and resumes counting operation (bit 3); sets input clock and clock frequency (bits 6?4) 8-bit f90h?f91h 8-bit write - only; (tmod0.3 is also 1 -bit writeable) "0" tcnt0 counter counts clock pulses matching the tmod0 frequency setting 8-bit f94h?f95h 8-bit read-only "0" tref0 reference stores reference value for the timer/counter 0 interval setting 8-bit f96h?f97h 8-bit write-only ffh toe0 flag controls timer/counter 0 output to the tclo0 pin 1-bit f92h.2 1-bit write-only "0"
timers and t imer/counters S3C72K8/p72k8 11- 12 clear set clear inverted clocks (fxx/2 10 , fxx/2 6 , fxx/2 4 , fxx) tcl0 clear clock selector tcnt0 tref0 8 8 8-bit comparator irqt0 tol0 p4.2 latch toe0 pm4.2 tmod0.7 tmod0.6 tmod0.5 tmod0.4 tmod0.3 tmod0.2 tmod0.1 tmod0.0 8 tclo0 serial i/o figure 11- 2. tc0 circuit diagram tc0 enable/disable procedure enable timer/counter 0 ? set tmod0.2 to logic one ? set the tc0 interrupt enable flag iet0 to logic one ? set tmod0.3 to logic one tcnt0, irqt0, and tol0 are cleared to logic zero, and timer/counter operation starts. disable timer/counter 0 ? set tmod0.2 to logic zero clock signal input to the counter register tcnt0 is halted. the current tcnt0 value is retained and can be read if necessary.
S3C72K8/p72k8 timers and timer/counters 11- 13 tc0 programmable timer/counter function timer/counter 0 can be programmed to generate interrupt requests at various intervals based on the selected system clock frequency. its 8-bit tc0 mode register tmod0 is used to activate the timer/counter and to select the clock frequency. the reference register tref0 stores the value for the number of clock pulses to be generated between interrupt requests. the counter register, tcnt0, counts the incoming clock pulses, which are compared to the tref0 value as tcnt0 is incremented. when there is a match (tref0 = tcnt0), an interrupt request is generated. to generate an interrupt request, the tc0 interrupt request flag (irqt0) is set to logic one, the status of tol0 is inverted, and the interrupt is generated. the content of tcnt0 is then cleared to 00h and tc0 continues counting. the interrupt request mechanism for tc0 includes an interrupt enable flag (iet0) and an interrupt request flag (irqt0). tc0 operation sequence the general sequence of operations for using tc0 can be summarized as follows: 1. set tmod0.2 to "1" to enable tc0. 2. set tmod0.6 to "1" to enable the system clock ( fxx) input. 3. set tmod0.5 and tmod0.4 bits to desired internal frequency (fxx/2 n ). 4. load a value to tref0 to specify the interval between interrupt requests. 5. set the tc0 interrupt enable flag ( iet0) to "1". 6. set tmod0.3 bit to "1" to clear tcnt0, irqt0, and tol0, and start counting. 7. tcnt0 increments with each internal clock pulse. 8. when the comparator shows tcnt0 = tref0, the irqt0 flag is set to "1" and an interrupt request is generated. 9. output latch (tol0) logic toggles high or low. 10. tcnt0 is cleared to 00h and counting resumes. 11. programmable timer/counter operation continues until tmod0.2 is cleared to "0".
timers and t imer/counters S3C72K8/p72k8 11- 14 tc0 event counter function timer/counter 0 can monitor or detect system 'events' by using the external clock input at the tcl0 pin as the counter source. the tc0 mode register selects rising or falling edge detection for incoming clock signals. the counter register tcnt0 is incremented each time the selected state transition of the external clock signal occurs. with the exception of the different tmod0.4?tmod0.6 settings, the operation sequence for tc0's event counter function is identical to its programmable timer/counter function. to activate the tc0 event counter function, ? set tmod0.2 to "1" to enable tc0; ? clear tmod0.6 to "0" to select the external clock source at the tcl0 pin; ? select tcl0 edge detection for rising or falling signal edges by loading the appropriate values to tmod0.5 and tmod0.4. ? p 4.2 must be set to input mode. table 11-5 . tmod0 settings for tcl0 edge detection tmod0.5 tmod0.4 tcl0 edge detection 0 0 rising edges 0 1 falling edges
S3C72K8/p72k8 timers and timer/counters 11- 15 tc0 clock frequency output using timer/counter 0, a modifiable clock frequency can be output to the tc0 clock output pin, tclo0. to select the clock frequency, load the appropriate values to the tc0 mode register, tmod0. the clock interval is selected by loading the desired reference value into the reference register tref0. to enable the output to the tclo0 pin, the following conditions must be met: ? tc0 output enable flag toe0 must be set to "1" ? i/o mode flag for p 4.2 must be set to output mode ("1") ? output latch value for p 4.2 must be set to "0" in summary, the operational sequence required to output a tc0-generated clock signal to the tclo0 pin is as follows: 1. load a reference value to tref0. 2. set the internal clock frequency in tmod0. 3. initiate tc0 clock output to tclo0 (tmod0.2 = "1"). 4. set p 4.2 mode flag to "1". 5. set p 4.2 output latch to "0". 6. set toe0 flag to "1". each time tcnt0 overflows and an interrupt request is generated, the state of the output latch tol0 is in verted and the tc0-generated clock signal is output to the tclo0 pin. + + programming tip ? tc0 signal output to the tclo0 pin output a 30 ms pulse width signal to the tclo0 pin: bits emb smb 15 ld ea,#79h ld tref0,ea ld ea,#4ch ld tmod0,ea ld ea,# 40 h ld pmg1 ,ea ; p 4.2 ? output mode bitr p4.2 ; p 4.2 clear bits toe0
timers and t imer/counters S3C72K8/p72k8 11- 16 tc0 serial i/o clock generation timer/count 0 can supply a clock signal to the clock selector circuit of the serial i/o interface for data shifter and clock counter operations. (these internal sio operations are controlled in turn by the sio mode register, smod). this clock generation function enables you to adjust data transmission rates across the serial interface. tc0 external input signal divider by selecting an external clock source and loading a reference value into the tc0 reference register, tref0, you can divide the incoming clock signal by the tref0 value and then output this modified clock frequency to the tclo0 pin. the sequence of operations used to divide external clock input can be summarized as follows: 1. load a signal divider value to the tref0 register. 2. clear tmod0.6 to "0" to enable external clock input at the tcl0 pin. 3. set tmod0.5 and tmod0.4 to desired tcl0 signal edge detection. 4. set port 3.0 mode flag (pm3.0) to output ("1"). 5. set p3.0 output latch to "0". 6. set toe0 flag to "1" to enable output of the divided frequency to t he tclo0 pin. tc0 mode register (tmod0) + + programming tip ? external tcl0 clock output to the tclo0 pin output external tcl0 clock pulse to the tclo0 pin (divided by four): external (tcl0) clock pulse tclo0 output pulse bits emb smb 15 ld ea,#01h ld tref0,ea ld ea,#0ch ld tmod0,ea ld ea,# 40 h ld pmg1 ,ea ; p 4.2 ? output mode bitr p4.2 ; p 4.2 clear bits toe0
S3C72K8/p72k8 timers and timer/counters 11- 17 tc0 mode register (tmod0) tmod0 is the 8-bit mode control register for timer/counter 0. it is addressable by 8-bit write instructions. one bit, tmod0.3, is also 1-bit writeable. reset clears all tmod0 bits to logic zero and disables tc0 operations. f90h tmod0.3 tmod0.2 "0" "0" f91h "0" tmod0.6 tmod0.5 tmod0.4 tmod0.2 is the enable/disable bit for timer/counter 0. when tmod0.3 is set to "1", the contents of tcnt0, irqt0, and tol0 are cleared, counting starts from 00h, and tmod0.3 is automatically reset to "0" for normal tc0 operation. when tc0 operation stops (tmod0.2 = "0"), the contents of the tc0 counter register tcnt0 are retained until tc0 is re-enabled. the tmod0.6, tmod0.5, and tmod0.4 bit settings are used together to select the tc0 clock source. this selection involves two variables: ? synchronization of timer/counter operations with either the rising edge or the falling edge of the clock sig nal input at the tcl0 pin, and ? selection of one of four frequencies, based on division of the incoming system clock frequency, for use in internal tc0 operation. table 11-6 . tc0 mode register (tmod0) organization bit name setting resulting tc0 function address tmod0.7 0 always logic zero tmod0.6 f91h tmod0.5 0,1 specify input clock edge and internal frequency tmod0.4 tmod0.3 1 clear tcnt0, irqt0, and tol0 and resume counting immedi ately (this bit is automatically cleared to logic zero immediately after counting resumes.) tmod0.2 0 disable timer/counter 0; retain tcnt0 contents f90h 1 enable timer/counter 0 tmod0.1 0 always logic zero tmod0.0 0 always logic zero
timers and t imer/counters S3C72K8/p72k8 11- 18 table 11-7 . tmod0.6, tmod0.5, and tmod0.4 bit settings tmod0.6 tmod0.5 tmod0.4 resulting counter source and clock frequency 0 0 0 external clock input (tcl0) on rising edges 0 0 1 external clock input (tcl0) on falling edges 1 0 0 fxx/2 10 (4.09 khz) 1 0 1 fxx /2 6 (65.5 khz) 1 1 0 fxx/2 4 (262 khz) 1 1 1 fxx = 4.19 mhz note : ' fxx' = selected system clock of 4.19 mhz. + + programming tip ? restarting tc0 counting operation 1. set tc0 timer interval to 4. 0 9 khz: bits emb smb 15 ld ea,#4ch ld tmod0,ea ei bits iet0 2. clear tcnt0, irqt0, and tol0 and restart tc0 counting operation: bits emb smb 15 bits tmod0.3
S3C72K8/p72k8 timers and timer/counters 11- 19 tc0 counter register (tcnt0) the 8-bit counter register for timer/counter 0, tcnt0, is read-only and can be addressed by 8-bit ram control instructions. reset sets all tcnt0 register values to logic zero (00h). whenever tmod0.3 is enabled, tcnt0 is cleared to logic zero and counting resumes. the tcnt0 register value is incremented each time an incoming clock signal is detected that matches the signal edge and frequency setting of the tmod0 register (specifically, tmod0.6, tmod0.5, and tmod0.4). each time tcnt0 is incremented, the new value is compared to the reference value stored in the tc0 reference buffer, tref0. when tcnt0 = tref0, an overflow occurs in the tcnt0 register, the interrupt request flag, irqt0, is set to logic one, and an interrupt request is generated to indicate that the specified timer/counter interval has elapsed. reference value = n 0 n ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ n count clock tref0 tcnt0 ~ ~ interval time tol0 timer start instruction (tmod0.3 is set) irqt0 set irqt0 set 1 2 n-1 0 1 2 n-1 0 1 2 3 match match ~ ~ figure 11- 3. tc0 timing diagram
timers and t imer/counters S3C72K8/p72k8 11- 20 tc0 reference register (tref0) the tc0 reference register tref0 is an 8-bit write-only register. it is addressable by 8-bit ram control instructions. reset initializes the tref0 value to 'ffh'. tref0 is used to store a reference value to be compared to the incrementing tcnt0 register in order to iden tify an elapsed time interval. reference values will differ depending upon the specific function that tc0 is being used to perform ? as a programmable timer/counter, event counter, clock signal divider, or arbitrary frequency output source. during timer/counter operation, the value loaded into the reference register is compared to the tcnt0 value. when tcnt0 = tref0, the tc0 output latch (tol0) is inverted and an interrupt request is generated to signal the interval or event. the tref0 value, together with the tmod0 clock frequency selection, determines the specific tc0 timer interval. use the following formula to calculate the correct value to load to the tref0 reference register: tc0 timer interval = (tref0 value + 1) 1 tmod0 frequency setting (tref0 value 1 0) tc0 output enable flag (toe0) the 1-bit timer/counter 0 output enable flag toe0 controls output from timer/counter 0 to the tclo0 pin. toe0 is addressable by 1-bit read and write instructions. (msb) (lsb) f92h "0" toe0 "0" "0" when you set the toe0 flag to "1", the contents of tol0 can be output to the tclo0 pin. whenever a reset occurs, toe0 is automatically set to logic zero, disabling all tc0 output. even when the toe0 flag is disabled, timer/counter 0 can continue to output an internally-generated clock frequency, via tol0 , to the serial i/o clock selector circuit . tc0 output latch (tol0) tol0 is the output latch for timer/counter 0. when the 8-bit comparator detects a correspondence between the value of the counter register tcnt0 and the reference value stored in the tref0 register, the tol0 value is inverted ? the latch toggles high-to-low or low-to-high. whenever the state of tol0 is switched, the tc0 signal is output. tc0 output may be directed to the tclo0 pin, or it can be output directly to the serial i/o clock selector circuit as the sck signal. assuming tc0 is enabled, when bit 3 of the tmod0 register is set to "1", the tol0 latch is cleared to logic zero, along with the counter register tcnt0 and the interrupt request flag, irqt0, and counting resumes immedi ately. when tc0 is disabled (tmod0.2 = "0"), the contents of the tol0 latch are retained and can be read, if necessary.
S3C72K8/p72k8 timers and timer/counters 11- 21 + + programming tip ? setting a tc0 timer interval to set a 30 ms timer interval for tc0, given fxx = 4.19 mhz, follow these steps. 1. select the timer/counter 0 mode register with a maximum setup time of 62.5 ms (assume the tc0 counter clock = fxx/2 10 , and tref0 is set to ffh): 2. calculate the tref0 value: 30 ms = tref0 value + 1 4.09 khz tref0 + 1 = 30 ms 244 s = 122.9 = 7ah tref0 value = 7ah ? 1 = 79h 3. load the value 79h to the tref0 register: bits emb smb 15 ld ea,#7 9h ld tref0,ea ld ea,#4ch ld tmod0,ea
timers and t imer/counters S3C72K8/p72k8 11- 22 watch timer overview the watch timer is a multi-purpose timer which consists of three basic components: ? 8-bit watch timer mode register (wmod) ? clock selector ? frequency divider circuit watch timer functions include real-time and watch-time measurement and interval timing for the main and sub - system clock. it is also used as a clock source for the lcd controller and for generating buzzer (buz) output. real-time and watch-time measurement to start watch timer operation, set bit 2 of the watch timer mode register (wmod.2) to logic one. the watch timer starts, the interrupt request flag irqw is automatically set to logic one, and interrupt requests commence in 0.5-second intervals. since the watch timer functions as a quasi-interrupt instead of a vectored interrupt, the irqw flag should be cleared to logic zero by program software as soon as a requested interrupt service routine has been executed. using a main system or subsystem clock source the watch timer can generate interrupts based on the main system clock frequency or on the subsystem clock. when the zero bit of the wmod register is set to "1", the watch timer uses the subsystem clock signal ( fxt) as its source; if wmod.0 = "0", the main system clock ( fx) is used as the signal source, according to the following formula: watch timer clock ( fw) = main system clock (fx) 128 = 32.768 khz ( fx = 4.19 mhz) this feature is useful for controlling timer-related operations during stop mode. when stop mode is engaged, the main system clock ( fx) is halted, but the subsystem clock continues to oscillate. by using the subsystem clock as the oscillation source during stop mode, the watch timer can set the interrupt request flag irqw to "1", thereby releasing stop mode. clock source generation for lcd controller the watch timer supplies the clock frequency for the lcd controller (f lcd ). there fore, if the watch timer is dis abled, the lcd controller does not operate.
S3C72K8/p72k8 timers and timer/counters 11- 23 buzzer output frequency generator the watch timer can generate a steady 2 khz, 4 khz, 8 khz, or 16 khz signal to the buz pin. to select the desired buz frequency , load the appropriate value to the wmod register. this output can then be used to actuate an external buzzer sound. to generate a buz signal, three conditions must be met: ? the wmod.7 register bit is set to "1" ? the output latch for i/o port 0.3 is cleared to "0" ? the port 0.3 output mode flag (pm0.3) set to 'output' mode timing tests in high-speed mode by setting wmod.1 to "1", the watch timer will function in high-speed mode, generating an interrupt every 3.91 ms. at its normal speed (wmod.1 = '0'), the watch timer generates an interrupt request every 0.5 sec onds. high- speed mode is useful for timing events for program debugging sequences. check subsystem clock level feature the watch timer can also check the input level of the subsystem clock by testing wmod.3. if wmod.3 is "1", the input level at the xt in pin is high; if wmod.3 is "0", the input level at the xt in pin is low.
timers and t imer/counters S3C72K8/p72k8 11- 24 fw/2 (16 khz) fw/8 (4 khz) fw/16 (2 khz) enable/ disable irqw f lcd fw/2 14 (2 hz) fw/2 7 fw (32.768 khz) fx = main-system clock (4.19 mhz) fxt = sub-system clock (32.768 khz) fw = watch timer frequency mux clock selector fxt fx/128 fw/4 (8 khz) frequency dividing circuit wmod.7 wmod.6 wmod.5 wmod.4 wmod.3 wmod.2 wmod.1 wmod.0 8 buz p0.3 latch pm0.3 selector circuit figure 11-4 . watch timer circuit diagram
S3C72K8/p72k8 timers and timer/counters 11- 25 watch timer mode register (wmod) the watch timer mode register wmod is used to select specific watch timer operations. it is 8-bit write-only addressable. an exception is wmod bit 3 (the xt in input level control bit) which is 1-bit read-only addressable. a reset automatically sets wmod.3 to the current input level of the subsystem clock, xt in (high, if logic one; low, if logic zero), and all other wmod bits to logic zero. f88h wmod.3 wmod.2 wmod.1 wmod.0 f89h wmod.7 "0" wmod.5 wmod.4 in summary, wmod settings control the following watch timer functions: ? watch timer clock selection (wmod.0) ? watch timer speed control (wmod.1) ? enable/disable watch timer (wmod.2) ? xt in input level control (wmod.3) ? buzzer frequency selection (wmod.4 and wmod.5) ? enable/disable buzzer output (wmod.7) table 11-8 . watch timer mode register (wmod) organization bit name values function address wmod.7 0 disable buzzer (buz) signal output f89h 1 enable buzzer (buz) signal output wmod.6 0 always logic zero wmod.5?.4 0 0 2 khz buzzer (buz) signal output 0 1 4 khz buzzer (buz) signal output 1 0 8 khz buzzer (buz) signal output 1 1 16 khz buzzer (buz) signal output wmod.3 0 input level to xt in pin is low f88h 1 input level to xt in pin is high wmod.2 0 disable watch timer; clear frequency dividing circuits 1 enable watch timer wmod.1 0 normal mode; sets irqw to 0.5 seconds 1 high-speed mode; sets irqw to 3.91 ms wmod.0 0 select (fx/128 ) as the watch timer clock (fw) 1 select subsystem clock as watch timer clock (fw) note : main system clock frequency ( fx) is assumed to be 4.19 mhz; subsystem clock ( fxt) is assumed to be 32.768 khz.
timers and t imer/counters S3C72K8/p72k8 11- 26 + + programming tip ? using the watch timer 1. select a subsystem clock as the lcd display clock, a 0.5 second interrupt, and 2 khz buzzer enable: bits emb smb 15 ld ea,#8h ld pmg1,ea ; p0.3 ? output mode bitr p0.3 ld ea,#85h ld wmod,ea bits iew 2. sample real-time clock processing method: clock btstz irqw ; 0.5 second check ret ; no, return ? ; yes, 0.5 second interrupt generation ? ? ; increment hour, minute, second
S3C72K8/p72k8 lcd controller/driv er 12 - 1 12 lcd controller/driver overview the S3C72K8 microcontroller can directly drive an up-to- 320 -dot ( 40 segments x 8 commons) lcd panel. its lcd block has the following components: ? lcd controller/d river ? display ram for storing display data ? 40 segment output pins (seg0?seg 35 ) ? 8 common output pins (com0? com7 ) ? five lcd operating power supply pins (v lc1 ?v lc5 ) ? v lc 5 pin for controlling the driver and bias voltage the frame frequency, duty and bias, and the segment pins used for display output, are determined by bit settings in the lcd mode register, lmod. the lcd control register, lcon, is used to turn the lcd display on and off, to switch current to the dividing resistors for the lcd display, and to output lcd clock (lcdck) and synchronizing signal (lcdsy) for lcd display expansion. data written to the lcd display ram can be transferred to the segment signal pins automatically without program control. when a subsystem clock is selected as the lcd clock source, the lcd display is enabled even during main clock stop and idle modes. 8 40 8 5 lcd controller/ driver v lc1 -v lc5 com0-com7 seg0-seg39 seg32-seg39/ p5.0-p5.7 8 data bus figure 12- 1. lcd function diagram
lcd controller/driver S3C72K8/p72k8 12 - 2 lcd circuit diagram seg39/p5.7 80 40 data bus lmod display ram (bank "1") lcon timing controller mux selector com control f lcd seg0 seg32p5.0 seg31 com7 com0 lcd voltage control v lc5 v lc1 p3.3 latch p3.2 latch pm3.2 pm3.2 lcdsy lcdck figure 12- 2. lcd circuit diagram
S3C72K8/p72k8 lcd controller/driv er 12 - 3 lcd ram address area ram addresses of bank 1 are used as lcd data memory. these locations can be addressed by 1-bit , 4-bit, or 8- bit instructions. when the bit value of a display segment is "1", the lcd display is turned on; when the bit value is "0", the display is turned off. display ram data are sent out through segment pins seg0?seg 40 using a direct memory access (dma) method that is synchronized with the f lcd signal. ram addresses in this location that are not used for lcd display can be allocated to general-purpose use. 1ffh.3 1fdh.3 1fbh.3 1f9h.3 1f7h.3 1f5h.3 1f3h.3 1f1h.3 1efh.3 1b7h.3 1b5h.3 1b3h.3 1b1h.3 1ffh.2 1fdh.2 1fbh.2 1f9h.2 1f7h.2 1f5h.2 1f3h.2 1f1h.2 1efh.2 1b7h.2 1b5h.2 1b3h.2 1b1h.2 1ffh.1 1fdh.1 1fbh.1 1f9h.1 1f7h.1 1f5h.1 1f3h.1 1f1h.1 1efh.1 1b7h.1 1b5h.1 1b3h.1 1b1h.1 1ffh.0 1fdh.0 1fbh.0 1f9h.0 1f7h.0 1f5h.0 1f3h.0 1f1h.0 1efh.0 1b7h.0 1b5h.0 1b3h.0 1b1h.0 1feh.3 1fch.3 1fah.3 1f8h.3 1f6h.3 1f4h.3 1f2h.3 1f0h.3 1eeh.3 1b6h.3 1b4h.3 1b2h.3 1b0h.3 1feh.2 1fch.2 1fah.2 1f8h.2 1f6h.2 1f4h.2 1f2h.2 1f0h.2 1eeh.2 1b6h.2 1b4h.2 1b2h.2 1b0h.2 1feh.1 1fch.1 1fah.1 1f8h.1 1f6h.1 1f4h.1 1f2h.1 1f0h.1 1eeh.1 1b6h.1 1b4h.1 1b2h.1 1b0h.1 1feh.0 1fch.0 1fah.0 1f8h.0 1f6h.0 1f4h.0 1f2h.0 1f0h.0 1eeh.0 1b6h.0 1b4h.0 1b2h.0 1b0h.0 seg31 seg3 seg2 seg1 seg0 com7 com6 com5 com4 com3 com2 com1 com0 seg39 seg38 seg37 seg36 seg35 seg34 seg33 seg32 p5.7 p5.6 p5.5 p5.4 p5.3 p5.2 p5.1 p5.0 figure 12- 3. lcd display data ram organization 1-bit output the eight pins (p5.0-p5.7) of the 40 segment output can be set in 4-bits for 1-bit level output by lmod.6 and lmod.7. the 1f0h.0 in lcd display ram is used as the output latch for p5.0, 1f2h.0 is for 5, 1, ?. and 1feh.0 is for p5.7.
lcd controller/driver S3C72K8/p72k8 12 - 4 table 12-1. common and segment pins per duty cycle duty common pins segment pins dot number 1/8 com0?com7 32?40 pins 256 dots?320 dots 1/4 com0?com3 128 dots?160 dots 1/3 com0?com2 96 dots?120 dots lcd control register (lcon) the lcd control register (lcon) is used to turn the lcd display on and off , to select duty , to output lcd seg expand signal for lcd display expansion, and to control the flow of current to dividing resistors in the lcd circuit. following a reset , all lcon values are cleared to "0". this turns the lcd display off and stops the flow of current to the dividing resistors. lcon lcon. 3 lcon.2 lcon.1 lcon.0 f8eh table 12-2. lcd control register (lcon) organization lcon bit setting description lcon.3 0 1/4 bias select 1 1/3 bias select lcon.2 0 disable lcdck andlcdsy signal outputs 1 enable lcdck andlcdsy signal outputs lcon.1 0 lcd display off (all com/seg pins are high output) 1 lcd display on lcon.0 0 turn off the internal lcd bias tr 1 turn on the internal lcd bias tr note s: 1. in case of lcon.0, you can turn on/off internal lcd bias tr. 2. in case of internal lcd bias when lcon.1?.0 = #00b, lcd display is turned off. when lcon.1?.0 = #11b, lcd display is turned on. 3. in case of external lcd bias when lcon.1?.0 = #00b and vlc5 = "high", lcd display is turned off. when lcon.1?.0 = #10b and vlc5 = "low", lcd display is turned on 4. to select lcd bias, you must use both the lcon.3 setting and an external lcd bias circuit connection. table 12- 3. lmod.1?0 bits settings lmod.1?0 com0? com7 seg0?seg 39 seg 32 /p 5.0 ?seg 39 /p 5.7 power supply to the dividing resistor 0, 0 all of the lcd dots off 1-bit output function on 0, 1 all of the lcd dots on 1, 1 common and segment signal output corresponds to display data (normal display mode)
S3C72K8/p72k8 lcd controller/driv er 12 - 5 lcd mode register (lmod) the lcd mode control register lmod is used to control display mode; lcd clock, segment or port output, and display on/off. lmod can be manipulated using 8-bit write instructions. the lcd clock signal, lcdck, determines the frequency of com signal scanning of each segment output. this is also referred to as the 'frame frequency. since lcdck is generated by dividing the watch timer clock ( fw), the watch timer must be enabled when the lcd display is turned on. the lcd display can continue to operate during idle and stop modes if a subsystem clock is used as the watch timer source. the lcd mode register lmod controls the output mode of the 8 pins used for normal outputs (p5.0?p5.7). bits lmod.7?5 define the segment output and normal bit output configuration. table 12- 4. lcd clock signal (lcdck) frame frequency lcdck 128 hz 256 hz 512 hz 1024 hz 2048 hz 4096 hz display duty cycle 1/8 ? ? 64 128 256 512 1/ 4 ? 64 128 256 512 ? 1/ 3 42.7 85.3 170.7 341.3 ? ? note: fw = 32.768 khz 1 frame com0
lcd controller/driver S3C72K8/p72k8 12 - 6 table 12- 5. lcd mode register (lmod) organization segment /output port selection bits lmod.7 lmod.6 seg39?36 seg35?32 total number of segment 0 0 seg port seg port 40 0 1 seg port output port 36 1 0 output port seg port 36 1 1 output port output port 32 lcd clock selection bits lmod. 5 lmod. 4 lcd clock (lcdck) 1/8 duty (com0?com7) 1/ 4 duty (com0?com 3 ) 1/ 3 duty (com0?com 2 ) 0 0 fxx/2 6 ( 512 hz) fxx/2 7 ( 256 hz) fxx/2 8 ( 128 hz) 0 1 fxx/2 5 ( 1024 hz) fxx /2 6 ( 512 hz) fxx /2 7 ( 256 hz) 1 0 fxx / 2 4 ( 2048 hz) fxx/ 2 5 ( 1024 hz) fxx/ 2 6 ( 512 hz) 1 1 fxx /2 3 ( 4096 hz) fxx/ 2 4 ( 2048 hz) fxx/ 2 5 ( 1024 hz) note: lcdck is supplied only when the watch timer operates. to use the lcd contro ller, bit-2 in the watch mode register wmod should be set to 1. display mode selection bits lmod.3 lmod.2 duty 0 0 1/8 duty (com0?com7 select) 1 0 1/4 duty (com0?com3 select) 1 1 1/3 duty (com0?com2 select) display mode selection bits lmod.1 lmod.0 function 0 0 all lcd dots off 0 1 all lcd dots on 1 0 normal display
S3C72K8/p72k8 lcd controller/driv er 12 - 7 lcd voltage dividing method power can be supplied without an external dividing resistor. figure 12-4 shows the bias connections for the S3C72K8 lcd drive power supply. 1/3 bais v cl1 v cl2 v cl3 v cl4 v cl5 S3C72K8 1/4 bais v cl1 v cl2 v cl3 v cl4 v cl5 S3C72K8 figure 12- 4. lcd bias circuit connection
lcd controller/driver S3C72K8/p72k8 12 - 8 application without contrast control if you use an internal transistor (lcon.0) to turn on/off 'lcd display', you can get a merit that peripheral circuits are simple. but in that case, you can't control lcd contrast. notes: 1. a 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for figure 12-5. 2. whe you turn off the lcd display using lcon settings, the amount of current flowing through the dividing resistors is reduced more than when you use lmod to turn off the display. 3. when lcon.1-0 = #00b, lcd display is turned off. when lcon.1-0 = #11b, lcd display is turned on. application with internal resistor v ss v dd S3C72K8 v cl1 v cl2 v cl3 v cl4 v cl5 lcon.0 (3) v lcd figure 12- 5. connection for lcd on/off using internal transistor
S3C72K8/p72k8 lcd controller/driv er 12 - 9 application with contrast control if only turn on/off 'lcd display' using external output pin, you can control lcd contrast using variable resistor. notes: 1. a 1/4 bias is assumed for the above circuits; a 1/3 bias is assumed for figure 12-6. 2. whe you turn off the lcd display using lcon settings, the amount of current flowing through the dividing resistors is reduced more than when you use lmod to turn off the display. 3. when lcon.1-0 = #00b and px.b = "high", lcd display is turned off. when lcon.1-0 = #10b and px.b = "low", lcd display is turned on. application with external resistor v ss v dd S3C72K8 v cl1 v cl2 v cl3 v cl4 v cl5 lcon.0 (always "0") v lcd px.b (3) v r figure 12-6 . connection for lcd on/off using external output pin
lcd controller/driver S3C72K8/p72k8 12 - 10 common (com) signals the common signal output pin selection (com pin selection) varies according to the selected duty cycle. ? in 1/8 duty mode, com0?com7 pins are selected ? in 1/4 duty mode, com0?com3 pins are selected ? in 1/3 duty mode, com0?com2 pins are selected segment (seg) signals the 40 lcd segment signal pins are connected to corresponding display ram locations at bank 1. bits of the display ram are synchronized with the common signal output pins. when the bit value of a display ram location is "1", a select signal is sent to the corresponding segment pin. when the display bit is "0", a 'no-select' signal is sent to the corresponding segment pin.
S3C72K8/p72k8 lcd controller/driv er 12 - 11 1 frame fr v dd v ss com0 com1 com2 com3 com4 com5 com6 com7 s e g 0 s e g 1 s e g 2 s e g 3 s e g 4 com1 seg0 com2 com0 seg0-com0 0 1 2 3 7 4 6 5 0 1 2 3 7 4 6 5 -v lc5 -v lc4 -v lc2 (-v lc3 ) -v lc1 v lc2 ( v lc3 ) v lc4 v lc5 v dd v lc1 v lc2 ( v lc3 ) v lc4 v lc5 v dd v lc1 v lc2 ( v lc3 ) v lc4 v lc5 v dd v lc1 v lc2 ( v lc3 ) v lc4 v lc5 v dd v lc1 v lc2 ( v lc3 ) v lc4 v lc5 v lc1 0v figure 12-7 . lcd signal waveforms (1/8 duty, 1/4 bias)
lcd controller/driver S3C72K8/p72k8 12 - 12 1 frame fr v dd v ss seg1 seg1-com0 0 1 2 3 7 4 6 5 0 1 2 3 7 4 6 5 v lc4 v lc5 v ss v lc1 v lc2 (v lc4 ) v lc1 v lc4 0v v lc5 -v lc5 -v lc4 -v lc1 v lc2 (v lc3 ) -v lc2 (-v lc3 ) figure 12-7 . lcd signal waveforms (1/8 duty, 1/4 bias) (continued)
S3C72K8/p72k8 lcd controller/driv er 12 - 13 1 frame v dd v ss 0 1 2 3 0 1 2 3 com0 com1 com2 com3 seg1 seg0 com0-seg0 com1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com2 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com3 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) + v lcd + 1/3 v lcd 0v - 1/3 v lcd - v lcd figure 12-8 . lcd signal waveforms (1/ 4 duty, 1/ 3 bias)
lcd controller/driver S3C72K8/p72k8 12 - 14 1 frame v dd v ss 0 1 2 com1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com2 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) seg1 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) com0-seg0 + v lcd com0 v ss v dd v lc1 ( v lc2 ) v lc3 ( v lc4 ) + 1/3 v lcd 0v - 1/3 v lcd - v lcd com0 com1 com2 seg2 seg1 seg0 0 1 2 figure 12-9 . lcd signal waveforms (1/ 3 duty, 1/ 3 bias)
S3C72K8/p72k8 comparator 13- 1 1 3 comparator overview p1.0,and p1.1 can be used as a analog input port for a comparator. the reference voltage for the 2-channel comparator can be supplied either internally or externally at p1.0. when an internal reference voltage is used, two channels (p1.0?p1.1) are used for analog inputs and the internal reference voltage is varied in 16 levels. if an external reference voltage is input at p1.0, the other p1.1 pins are used for analog input. when a conversion is completed, the result is saved in the comparison result register cmpreg. the initial values of the cmpreg are undefined and the comparator operation is disabled by a reset . the comparator module has the following components: ? comparator ? intern al reference voltage generator (4-bit resolution) ? external reference voltage source at p1.0 ? comparator mode register (cmod) ? comparison result register (cmpreg)
comparator S3C72K8/p72k8 13- 2 p1.1/cin1/int1 p1.0/cin0/int0 + - mux mux v ref (external) comparison result register (cmpreg) 4 8 v dd mux 1/2r r r 1/2r v ref (internal) internal bus notes: 1. int occures only for digital input selecting: for analog input, any int doesn't. 2. the cpmparison results of cin0, and cin1 are respectively stored in cmpreg.0 and cmpreg.1. cmod.7 cmod.6 cmod.5 0 cmod.3 cmod.2 cmod.1 cmod.0 figure 13- 1. comparator circuit diagram
S3C72K8/p72k8 comparator 13- 3 comparator mode register (cmod) the comparator mode register cmod is an 8-bit register that is used to select the operation mode of the comparator. it is mapped to addresses fd 2 h?fd 3 h and can be manipulated using 8-bit memory instructions. based on the cmod.5 bit setting, an internal or an external reference voltage is input for the comparator, as follows: when cmod.5 is set to logic zero: ? a reference voltage is selected by the cmod.0 to cmod.3 bit settings. ? p 1.0 to p1.1 are used as analog input pins. ? the internal digital to analog converter generates 16 reference voltages. ? the comparator can detect 150 mv differences between the reference voltage and the analog input voltages. ? comparator results are written into bit - 0 to bit -2 of the comparison result register (cmpreg). when cmod.5 is set to logic one: ? an external reference voltage is supplied from p 1.0 /cin 0 . ? p 1.1 is used as the analog input pins. ? the comparator can detect 150 mv differences between the reference voltage and the analog input voltages. ? bit s 0 and 1 in the cmpreg register contain the results. bit 6 in the cmod register controls conversion time while bit 7 enables or disables comparator operation to reduce power consumption. a reset signal clears all bits to logic zero, causing the comparator to enter stop mode. cmod.7 cmod.6 cmod.5 "0" cmod.3 cmod.2 cmod.1 cmod.0 fd6h-fd7h reference voltage (v ref ) selection; v dd x (n + 0.5)/16, n = 0 to 15 1: cin0; external reference, cin1; analog input 0: internal reference, cin0-1; analog input 1: conversion time (4 x 2 5 /fx, 30.5 m s @4.19 mhz) 0: conversion time (4 x 2 6 /fx, 244.4 m s @4.19 mhz) 1: comparator operation enable 0: comparator operation disable figure 13- 2. comparator mode register (cmod) organization
comparator S3C72K8/p72k8 13- 4 port 1 mode register (p 1 mod) p 1 mod register settings determine if p 1.0 and p1.1 are used for analog or digital input. the p 1 mod register is 4-bit write-only register. p 1 mod is mapped to address fe 2 h. a reset operation initializes all p 1 mod register values to zero, configuring p 1.0 and p1.1 as a digital input port. fe 2 h "0" "0" p 1 mod.1 p 1 mod.0 when a p 1 mod bit is set to "0", the corresponding pin is configured as a digital input pin. when set to "1", it is configured as an analog input pin: p 1 mod.0 for p 1.0, and p 1 mod.1 for p 1 .1. comparator operation the comparator compares analog voltage input at cin0?cin 2 with an external or internal reference voltage (v ref ) that is selected by the cmod register. the result is written to the comparison result register cmpreg at address fd4h. the comparison result at internal reference is calculated as follows: if "1" analog input voltage 3 v ref + 150 mv if "0" analog input voltage v ref ? 150 mv to obtain a comparison result, the data must be read out from the cmpreg register after v ref is updated by changing the cmod value after a conversion time has elapsed. comparison result (cmpreg) comparsion time (cmpclk x 8) 1 1 0 unkwon unkwon comparator clock (cmpclk, fx/16, fx/128) reference voltage (v ref ) analog input voltage (cin0-2) comparison start comparison end figure 13- 3. conversion characteristics
S3C72K8/p72k8 comparator 13- 5 + + programming tip ? programming the comparator the following code converts the analog voltage input at the cin0?cin 1 pins into 4-bit digital code. bitr emb ld a,# 0h ld p 1 mod,a ; analog input selection (cin0 ?cin 1 ) ld ea,#0cxh ; x = 0 ? f, comparator enable ; internal reference, conversion time ( 7.6 m s at 4.19 mhz) ld cmod,ea ld a,#0h wait incs a jr wait ld a,cmpreg ; r ead the result ld p2,a ; output the result from port 2
S3C72K8/p72k8 serial i/o interfac e 14- 1 1 4 serial i/o interface overview the serial i/o interface (sio) has the following functional components: ? 8-bit mode register (smod) ? clock selector circuit ? 8-bit buffer register (sbuf) ? 3-bit serial clock counter using the serial i/o interface, 8-bit data can be exchanged with an external device. the transmission frequency is controlled by making the appropriate bit settings to the smod register. the serial interface can run off an internal or an external clock source, or the tol 0 signal that is generated by the 8-bit timer/counter, tc 0 . if the tol 0 clock signal is used, you can modify its frequency to adjust the serial data transmission rate. serial i/o operation sequence the general operation sequence of the serial i/o interface can be summarized as follows: 1. set sio mode to transmit-and-receive or to receive-only. 2. select msb-first or lsb-first transmission mode. 3. set the sck clock signal in the mode register, smod. 4. set sio interrupt enable flag (ies) to "1". 5. initiate sio transmission by setting bit 3 of the smod to "1". 6. when the sio operation is complete, irqs flag is set and an interrupt is generated.
serial i/o interface s3c 72k8/p72k8 14- 2 over flow so clear smod.7 q r s p0.0/ sck si irqs note : instruction execution bits (note) 8 8 sbuf (8-bit) lsb or msb first clock selector tol0 cpu clk fxx/2 10 fxx/2 4 smod.6 smod.5 - smod.3 smod.2 smod.1 smod.0 q0 q1 q2 3-bit counter r q d ck internal bus internal bus figure 14- 1. serial i/o interface circuit diagram
S3C72K8/p72k8 serial i/o interfac e 14- 3 serial i/o mode register (smod) the serial i/o mode register, smod, is an 8-bit register that specifies the operation mode of the serial interface. its reset value is logical zero. smod is organized in two 4-bit registers, as follows: fe0h smod.3 smod.2 smod.1 smod.0 fe1h smod.7 smod.6 smod.5 0 smod register settings enable you to select either msb-first or lsb-first serial transmission, and to operate in transmit-and-receive mode or receive-only mode. smod is a write-only register and can be addressed only by 8- bit ram control instructions. one exception to this is smod.3, which can be written by a 1-bit ram control instruction. when smod.3 is set to 1, the contents of the serial interface interrupt request flag, irqs, and the 3- bit serial clock counter are cleared, and sio operations are initiated. when the sio transmission starts, smod.3 is cleared to logical zero. table 14- 1. sio mode register (smod) organization smod.0 0 most significant bit (msb) is transmitted first 1 least significant bit (lsb) is transmitted first smod.1 0 receive-only mode 1 transmit-and-receive mode smod.2 0 disable the data shifter and clock counter; retain contents of irqs flag when serial transmission is halted 1 enable the data shifter and clock counter; set irqs flag to "1" when serial transmission is halted smod.3 1 clear irqs flag and 3-bit clock counter to "0"; initiate transmission and then reset this bit to logic zero smod.4 0 bit not used; value is always "0" smod.7 smod.6 smod.5 clock selection r/w status of sbuf 0 0 0 external clock at sck pin sbuf is enabled when sio operation is halted or when sck goes high. 0 0 1 use tol 0 clock from tc 0 0 1 x cpu clock: fxx/4, fxx/8, fxx/64 enable sbuf read/write 1 0 0 4.09 khz clock: fxx/2 10 sbuf is enabled when sio operation is halted or when sck goes high. 1 1 1 262 khz clock: fxx/2 4 notes : 1. ' fxx' = system clock; 'x' means 'don't care' . 2. khz frequency ratings assume a system clock ( fxx) running at 4.19 mhz. 3. the sio clock selector circuit cannot select a fxx/2 4 clock if the cpu clock is fxx/64 . 4. it must be selected msb-first or lsb-first transmission mode before loading a data to sbuf.
serial i/o interface s3c 72k8/p72k8 14- 4 serial i/o timing diagrams di7 di6 di5 di4 di3 di2 di1 di0 do6 do5 do4 do3 do2 do1 do0 do7 transmit complete set smod.3 so si sck irqs figure 14- 2. sio timing in transmit/receive mode di7 di6 di5 di4 di3 di2 di1 di0 transmit complete set smod.3 high impedance si sck irqs so figure 14- 3. sio timing in receive-only mode
S3C72K8/p72k8 serial i/o interfac e 14- 5 serial i/o buffer register (sbuf) the serial i/o buffer register ,sbuf, can be read or written using 8-bit ram control instructions. following a reset , the value of sbuf is undetermined. when the serial interface operates in transmit-and-receive mode (smod.1 = "1"), transmit data in the sio buffer register are output to the so pin (p0.1) at the rate of one bit for each falling edge of the sio clock. receive data are simultaneously input from the si pin (p0.2) to sbuf at the rate of one bit for each rising edge of the sio clock. when receive-only mode is used, incoming data are input to the sio buffer at the rate of one bit for each rising edge of the sio clock. + + programming tip ? setting transmit/receive modes for serial i/o 1. transmit the data value 48h through the serial i/o interface using an internal clock frequency of fxx/2 4 and in msb-first mode: bits emb smb 15 ld ea,#03h ld pmg1,ea ; p0.0/ sck and p0.1 / so ? output ld ea,#48h ld sbuf,ea ld ea,#0eeh ld smod,ea ; sio data transfer external device sck /p0.0 so/p0.1 [S3C72K8] 2. use cpu clock to transfer and receive serial data at high speed: bit r emb ld ea,#03h ld pmg1,ea ; p0.0/ sck and p0.1/so ? output, p0.2/si ? input ld ea ,tdata ; tdata address = bank0 (20h?7fh) ld sbuf,ea ld ea,#4fh ld smod,ea ; sio start bitr ies stest btstz irqs jr stest ld ea,sbuf smb 0 ld rdata,ea ; rdata address = bank0 (20h?7fh)
serial i/o interface s3c 72k8/p72k8 14- 6 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 3. transmit and receive an internal clock frequency of 4.09 khz (at 4.19 mhz) in lsb-first mode: bit r emb ld ea,#03h ld pmg1,ea ; p0.0/ sck and p0.1/so ? output, p0.2/si ? input ld ea,tdata ; tdata address = bank0 (20h?7fh) ld sbuf, ea ld ea,#8fh ld smod,ea ; sio start ei bits ies . . ints push sb ; store smb, srb push ea ; store ea bitr emb ld ea,tdata ; ea ? transmit data ; tdata address = bank0 (20h?7fh) xch ea,sbuf ; transmit data ? receive data ld rdata,ea ; rdata address = bank0 (20h?7fh) bits smod.3 ; sio start pop ea pop sb iret external device sck /p0.0 so/p0.1 si/p0.2 [S3C72K8]
S3C72K8/p72k8 serial i/o interfac e 14- 7 + + programming tip ? setting transmit/receive modes for serial i/o (continued) 4. transmit and receive an external clock in lsb-first mode: bit r e mb ld ea,#02h ld pmg1,ea ; p0.1/so ? output, p0.0 / sck and p0.2/si ? input ld ea,tdata ; tdata address = bank0 (20h?7fh) ld sbuf,ea ld ea,#0fh ld smod,ea ; sio start ei bits ies . . ints push sb ; store smb, srb push ea ; store ea bitr emb ld ea,tdata ; ea ? transmit data ; tdata address = bank0 (20h?7fh) xch ea,sbuf ; transmit data ? receive data ld rdata,ea ; rdata address = bank0 (20h?7fh) bits smod.3 ; sio start pop ea pop sb iret high speed sio transmission external device sck /p0.0 so/p0.1 si/p0.2 [S3C72K8]
S3C72K8/p72k8 electrical data 15- 1 1 5 electrical data overview in this section, information on S3C72K8 electrical characteristics is presented as tables and graphics. the information is arranged in the following order: standard electrical characteristics ? abso lute maximum ratings ? d.c. electrical characteristics ? main system clock oscillator characteristics ? subsystem clock oscillator characteristics ? i/o capacitance ? comparator electrical characteristics ? a.c. electrical characteristics ? o perating voltage range stop mode characteristics and timing waveforms ? ram data retention supply voltage in stop mode ? stop mode release timing when initiated by reset ? stop mode release timing when initiated by an interrupt request miscellaneous timing waveforms ? a .c timing measurement point s ? clock timing measurement at x in ? clock timing measurement at xt in ? tcl timing ? input timing for reset signal ? input timing for external interrupts ? serial data transfer timing
electrical data S3C72K8/p72k8 15- 2 table 15- 1. absolute maximum ratings (t a = 25 c) parameter symbol conditions rating units supply voltage v dd ? ? 0.3 to + 6.5 v input voltage v i 1 all i/o pins active ? 0.3 to v dd + 0.3 v output voltage v o ? ? 0.3 to v dd + 0.3 v output current high i oh one i/o p in active ? 15 ma all i/o pins active ? 3 5 output current low i ol one i/o pin active + 30 (peak value) ma + 15 (note) all i/o port, total + 100 (peak value) + 60 (note) operating temperature t a ? ? 40 to + 85 c storage temperature t stg ? ? 65 to + 150 c note: the values for output current low ( i ol ) are calculated as peak value duty .
S3C72K8/p72k8 electrical data 15- 3 table 15- 2. d.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units input high voltage v ih1 ports 2, 3, p4.0 and p4.2 0.7 v dd ? v dd v v ih2 ports 0, 1, p4.1 and reset 0.8 v dd v dd v ih3 x in , x out and xt in v dd ? 0. 1 v dd input low voltage v il1 ports 2, 3, p4.0 and p4.2 ? ? 0.3 v dd v v il2 ports 0, 1, p4.1 and reset 0.2 v dd v il3 x in , x out and xt in 0. 1 output high voltage v oh 1 v dd = 4.5 v to 5.5 v i oh = ? 3 m a ports 0, 2 , 3 and 4 v dd ? 2.0 v dd ? 0.4 ? v v oh 2 v dd = 4.5 v to 5.5 v i oh = ? 100 m a ports 5 v dd ? 2.0 ? ? output low voltage v ol 1 v dd = 4.5 v to 5.5 v i ol = 15 ma ports 0, 2 , 3 and 4 ? 0.4 2 v v ol 2 v dd = 4.5 v to 5.5 v i oh = ? 100 m a ports 5 ? ? 1 input high leakage current i lih1 v i n = v dd all input pins except those specified below for i lih2 ? ? 3 m a i lih2 v i n = v dd x in , x out and xt in 20 input low leakage current i lil1 v i n = 0 v all input pins except x in , x out , xt in , and reset ? ? ? 3 m a i lil2 v i n = 0 v x in , x out and xt in ? 20 output high leakage current i loh v o = v dd all output pins ? ? 3 m a output low leakage current i lol v o = 0 v all output pins ? ? ? 3 m a
electrical data S3C72K8/p72k8 15- 4 table 15- 2. d.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units pull-up resistor r l i v i n = 0 v; v dd = 5 v 10 % port s 0 -4 15 40 80 k w v dd = 3 v 10 % 30 80 200 r l 2 v i n = 0 v; v dd = 5 v 10 % reset 150 220 350 v dd = 3 v 10 % 300 400 800 lcd voltage dividing resistor r lcd ? 40 60 90 k w | v dd -com i | voltage drop (i = 0 -7 ) v dc v dd = 2.7 v to 5.5 v ? 15 m a per common pin ? ? 120 mv | v dd -segx| voltage drop (x = 0 -39 ) v ds v dd = 2.7 v to 5.5 v ? 15 m a per segment pin ? ? 120 v lc 1 output voltage v lc 2 v dd = 2.0 v to 5.5 v (1) lcd clock = 0 hz, v lc 5 = 0 v 0.8 v dd ? 0.2 0.8 v dd 0.8 v dd + 0.2 v v lc 2 output voltage v lc 3 0.6 v dd ? 0.2 0.6 v dd 0.6 v dd + 0.2 v lc 3 output voltage v lc 4 0.4 v dd ? 0.2 0.4 v dd 0.4 v dd + 0.2 v lc 4 output voltage v lc 5 0.2 v dd ? 0.2 0.2 v dd 0.2 v dd + 0.2
S3C72K8/p72k8 electrical data 15- 5 table 15- 2. d.c. electrical characteristics (concluded) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units supply current ( 1 ) i dd1 ( 2 ) v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz ? 3.5 2.5 8.0 5.5 ma v dd = 3 v 10% 6.0 mhz 4.19 mhz 1.8 1.3 4.0 3.0 i dd2 ( 2 ) idle mode v dd = 5 v 10% c rystal oscillator c1 = c2 = 22 pf 6.0 mhz 4.19 mhz 1.3 1.2 2.5 1.8 v dd = 3 v 10% 6.0 mhz 4.19 mhz 0.5 0.4 1.5 1.0 i dd3 ( 3 ) v dd = 3 v 10% 32 khz crystal oscillator ? 15 30 ma i dd4 ( 3 ) idle mode; v dd = 3 v 10% 32 khz crystal oscillator 6 15 i dd5 stop mode; v dd = 5 v 10% scmod = 0000b xt in = 0v 2.5 5 stop mode; v dd = 3 v 10% 0.5 3 v dd = 5 v 10% scmod = 0100b 0.2 3 v dd = 3 v 10% 0.1 2 notes: 1 . currents in the following circuits are not included; on-chip pull-up resistors, internal lcd voltage dividing resistors, output port drive currents, comparator. 2 . data includes power consumption for subsy stem clock oscillation. 3 . when the system clock control register, scmod, is set to 1001b, main system clock oscillation stops and the subsystem clock is used. 4. every values in this table is measured when the power control register (pcon) is set to "0011b".
electrical data S3C72K8/p72k8 15- 6 table 15- 3. main system clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units ceramic oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) stabilization occurs when v dd is equal to the minimum oscillator voltage range. ? ? 4 ms crystal oscillator x in c1 c2 x out oscillation frequency (1) ? 0.4 ? 6.0 mhz stabilization time (2) v dd = 4.5 v to 5.5 v ? ? 10 ms v dd = 2.7 v to 4 .5 v ? ? 30 external clock x in x out x in input frequency (1) ? 0.4 ? 6.0 mhz x in input high and low level width (t xh , t xl ) ? 83.3 ? 1250 ns rc oscillator x in x out r frequency r = 10 k w , v dd = 5 v ? 2 ? mhz r = 30 k w , v dd = 3 v ? 1 ? notes: 1. oscillation frequency and x in i nput frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs, or when stop mode is terminated.
S3C72K8/p72k8 electrical data 15- 7 table 15- 4. subsystem clock oscillator characteristics (t a = ? 40 c + 85 c, v dd = 2.0 v to 5.5 v ) oscillator clock configuration parameter test condition min typ max units crystal oscillator xt in c1 c2 xt out oscillation frequency (1) ? 32 32.768 35 khz stabilization time (2) v dd = 4.5 v to 5.5 v ? 1.0 2 s v dd = 2.0 v to 4 .5 v ? ? 10 external clock xt in xt out xt in input frequency (1) ? 32 ? 100 khz xt in input high and low level width (t xtl , t xth ) ? 5 ? 15 m s notes: 1. oscillation frequency and xt in input frequency data are for oscillator characteristics only. 2. stabilization time is the interval required for oscillating stabilization after a power-on occurs.
electrical data S3C72K8/p72k8 15- 8 table 15- 5. input/output capacitance (t a = 25 c, v dd = 0 v ) parameter symbol condition min typ max units input capacitance c in f = 1 mhz; unmeasured pins are returned to v ss ? ? 15 pf output capacitance c out ? ? 15 pf i/o capacitance c io ? ? 15 pf table 15-6 . comparator electrical characteristics (t a = ? 40 c + 85 c, v dd = 4.0 v to 5.5 v ) parameter symbol condition min typ max units input voltage range ? ? 0 ? v dd v reference voltage range v ref 0 v dd v input voltage accuracy v cin ? 150 mv input leakage current i cin , i ref ? 3 3 m a
S3C72K8/p72k8 electrical data 15- 9 table 15-7 . a.c. electrical characteristics (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units instruction cycle time (note) t cy v dd = 2.7 v to 5.5 v 0.67 ? 64 m s v dd = 2.0 v to 5 .5 v 0.95 ? 64 with subsystem clock (fxt) 114 122 125 tcl0 input frequency f ti0 , f ti1 v dd = 2.7 v to 5.5 v 0 ? 1 .5 mhz v dd = 2.0 v to 5 .5 v 1 tcl0 input high, low width t tih0 , t til0 t tih1 , t til1 v dd = 2.7 v to 5.5 v 0.48 ? ? m s v dd = 2.0 v to 5 .5 v 1.8 sck cycle time t kcy v dd = 2.7 v to 5.5 v external sck source 800 ? ? ns internal sck source 650 v dd = 2.0 v to 5 .5 v external sck source 3200 internal sck source 3800 sck high, low width t kh , t kl v dd = 2.7 v to 5.5 v external sck source 325 ? ? ns internal sck source t kcy /2 ? 50 v dd = 2.0 v to 5 .5 v external sck source 1600 internal sck source t kcy / 2 ? 150 si setup time to sck high t sik v dd = 2.7 v to 5.5 v external sck source 100 ? ? ns internal sck source 150 v dd = 2.0 v to 5 .5 v external sck source 150 internal sck source 500 si hold time to sck high t ksi v dd = 2.7 v to 5.5 v external sck source 400 ? ? ns internal sck source 400 v dd = 2.0 v to 5 .5 v external sck source 600 internal sck source 500 note: unless otherwise specified, instruction cycle time condition values assume a main system clock ( fx ) source.
electrical data S3C72K8/p72k8 15- 10 table 15-7 . a.c. electrical characteristics (continued) (t a = ? 40 c to + 85 c, v dd = 2.0 v to 5.5 v ) parameter symbol conditions min typ max units output delay for sck to so t kso v dd = 2.7 v to 5.5 v external sck source ? ? 300 ns internal sck source 250 v dd = 2.0 v to 5.5 v external sck source 1000 internal sck source 1000 interrupt input high, low width t inth , t intl int0 , int1, int2, int4, k0? k3 10 ? ? m s reset input low width t rsl input 10 ? ? m s 1.5 mhz cpu clock 1.05 mhz 15.6 khz main oscillator frequency (divided by 4) 4.2 mhz 6 mhz 1 2 3 4 5 6 7 supply voltage (v) cpu clock = 1/n x oscillator frequency (n = 4, 8 or 64) 2.0 v 2.7 v figure 15- 1. standard operating voltage range
S3C72K8/p72k8 electrical data 15- 11 table 15-8. ram data retention supply voltage in stop mode (t a = ? 40 c to + 85 c) parameter symbol conditions min typ max unit data retention supply voltage v dddr ? 2.0 ? 5.5 v data retention supply current i dddr v dddr = 2.0 v ? 0.1 10 m a release signal set time t srel ? 0 ? ? m s oscillator stabilization wait time (1) t wait released by reset ? 2 17 / fx ? ms released by interrupt ? (2) ? notes : 1. during oscillator stabilization wait time, all cpu operations must be stopped to avoid instability during oscillator start-up. 2. use the basic timer mode register (bmod) interval timer to delay execution of cpu instructions during the wait time.
electrical data S3C72K8/p72k8 15- 12 timing waveforms execution of stop instrction internal reset operation ~ ~ v dddr ~ ~ stop mode idle mode normal mode data retention mode t srel t wait reset v dd figure 15-2. stop mode release timing when initiated by reset reset execution of stop instrction v dddr ~ ~ data retention mode v dd normal mode ~ ~ stop mode idle mode t srel t wait power-down mode terminating signal (interrupt request) figure 15-3. stop mode release timing when initiated by interrupt request
S3C72K8/p72k8 electrical data 15- 13 0.8 v dd 0.2 v dd 0.8 v dd 0.2 v dd measurement points figure 15-4 . a.c. timing measurement points (except for x in and xt in ) x in t xh t xl 1/fx v dd - 0.1 v 0.1 v figure 15-5 . clock timing measurement at x in xt in t xth t xtl 1/fxt v dd - 0.1 v 0.1 v figure 15-6 . clock timing measurement at xt in
electrical data S3C72K8/p72k8 15- 14 tcl0 t tih t til 1/f ti 0.8 v dd 0.2 v dd figure 15-7 . tc l timing reset t rsl 0.2 v dd figure 15-8 . input timing for reset reset signal int0, 1, 2, 4, k0 to k3 t inth t intl 0.8 v dd 0.2 v dd figure 15-9 . input timing for external interrupts and quasi-interrupts
S3C72K8/p72k8 electrical data 15- 15 output data input data sck t kh t kcy t kl 0.8 v dd 0.2 v dd t kso t si k t ksi 0.8 v dd 0.2 v dd si so figure 15- 1 0 . serial data transfer timing
S3C72K8/p72k8 mecha nical data 16- 1 16 mechanical data overview the S3C72K8 microcontroller is currently available in a 80-pin qfp package. 80-qfp-1420c #80 20.00 0.20 23.90 0.30 14.00 0.20 17.90 0.30 #1 0.80 0.35 + 0.10 note : dimensions are in millimeters. 0.15 max (0.80) 0.15 + 0.10 - 0.05 0-8 0.10 max 0.80 0.20 0.05 min 2.65 0.10 3.00 max 0.80 0.20 figure 16-1. 80-qfp-1420c package dimensions
S3C72K8/p72k8 s3p72k8 otp 17- 1 17 s3p72k8 otp overview the s3p72k8 single-chip cmos microcontroller is the otp (one time programmable) version of the S3C72K8 microcontroller. it has an on-chip otp rom instead of masked rom. the eprom is accessed by serial data format. the s3p72k8 is fully compatible with the S3C72K8, both in function and in pin configuration except rom size. because of its simple programming requirements, the s3p72k8 is ideal for use as an evaluation chip for the S3C72K8.
s3p72k8 otp S3C72K8 /p72k8 17- 2 s3p72k8 (80-qfp-1420c) p5.6/seg38 p5.7/seg39 v lc1 v lc2 v lc3 v lc4 v lc5 p0.0/ sck /k0 p0.1/so/k1 sdat /p0.2/si/k2 sclk /p0.3/buz/k3 v dd /v dd v ss /v ss x out x in v pp /test xt in xt out reset reset /reset p1.0/int0/cin0 p1.1/int1/cin1 p1.1/int2 p1.3/int4 p2.0 seg21 seg20 seg19 seg18 seg17 seg16 seg15 seg14 seg13 seg12 seg11 seg10 seg9 seg8 seg7 seg6 seg5 seg4 seg3 seg2 seg1 seg0 com7 com6 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 com5 com4 com3 com2 com1 com0 tclo0/p4.2 tcl0/p4.1 clo/p4.0 lcdck/p3.3 lcdsy/p3.2 p3.1 p3.0 p2.3 p2.2 p2.1 seg22 seg23 seg24 seg25 seg26 seg27 seg28 seg29 seg30 seg31 seg32/p5.0 seg33/p5.1 seg34/p5.2 seg35/p5.3 seg36/p5.4 seg37/p5.5 figure 17-1. s3p72k8 pin assignments (80-qfp package)
S3C72K8/p72k8 s3p72k8 otp 17- 3 table 17-1. descriptions of pins used to read/write the eprom main chip during programming pin name pin name pin no. i/o function p0.2 sdat 10 i/o serial data pin. output port when reading and input port when writing. can be assigned as a input/push-pull output port. p0.3 sclk 11 i serial clock pin. input only pin. test v pp 16 i power supply pin for eprom cell writing (indicates that otp enters into the writing mode). when 12.5 v is applied, otp is in writing mode and when 5 v is applied, otp is in reading mode. (option) reset reset 19 i chip initialization v dd /v ss v dd /v ss 12/13 i logic power supply pin. v dd should be tied to +5 v during programming. table 17-2. comparison of s3p72k8 and S3C72K8 features characteristic s3p72k8 S3C72K8 program memory 8-kbyte eprom 8-kbyte mask rom operating voltage (v dd ) 2.0 v to 5.5 v 2.0 v to 5.5 v otp programming mode v dd = 5 v, v pp (test) = 12.5v pin configuration 80 qfp 80 qfp eprom programmability user program 1 time programmed at the factory operating mode characteristics when 12.5 v is supplied to the v pp (test) pin of the s3p72k8, the eprom programming mode is entered. the operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in table 17-3 below. table 17-3. operating mode selection criteria v dd v pp (test) reg/ mem address (a15-a0) r/w mode 5 v 5 v 0 0000h 1 eprom read 12.5 v 0 0000h 0 eprom program 12.5 v 0 0000h 1 eprom verify 12.5 v 1 0e3fh 0 eprom read protection note : "0" means low level; "1" means high level.
S3C72K8/p72k8 development tools 18- 1 18 development tools overview samsung provides a powerful and easy-to-use development support system in turnkey form. the development support system is configured with a host system, debugging tools, and support software. for the host system, any standard computer that operates with ms-dos as its operating system can be used. one type of debugging tool including hardware and software is provided: the sophisticated and powerful in-circuit emulator, smds2+, for s3c7 , s3c9 , s3c8 families of microcontrollers. the smds2+ is a new and improved version of smds2. samsung also offers support software that includes debugger, as s embler, and a program for setting options. shine samsung host interface for in - c ircuit emulator, shine, is a multi-window based debugger for smds2+. shine provides pull-down and pop-up menus, mouse support, function/hot keys, and context-sensitive hyper-linked help. it has an advanced, multiple-windowed user interface that emphasizes ease of use. each window can be sized, moved, scrolled, highlighted, added, or removed completely. sama assembler the samsung arrangeable microcontroller (sam) assembler, sama, is a universal assembler, and generates object code in standard hexadecimal format. assembled program code includes the object code that is used for rom data and required smds program control data. to assemble programs, sama requires a source file and an auxiliary definition (def) file with device specific information. sasm 57 the sasm 57 is an relocatable assembler for samsung's s3c7 -series microcontrollers. the sasm 57 takes a source file containing assembly language statements and translates into a corresponding source code, object code and comments. the sasm 57 supports macros and conditional assembly. it runs on the ms-dos operating system. it produces the relocatable object code only, so the user should link object file. object files can be linked with other object files and loaded into memory. hex2rom hex2rom file generates rom code from hex file which has been produced by assembler. rom code must be needed to fabricate a microcontroller which has a mask rom. when generating the rom code (.obj file) by hex2rom, the value 'ff' is filled into the unused rom area up to the maximum rom size of the target device automatically. target boards target boards are available for all s3c7 -series microcontrollers. all required target system cables and adapters are included with the device-specific target board. otp s one time programmable microcontroller ( otp) for the S3C72K8 microcontroller and otp programmer (gang) are now available.
development tools S3C72K8/p72k8) 18- 2 bus smds2+ rs-232c pod probe adapter prom/otp writer unit ram break/display unit trace/timer unit sam4 base unit power supply unit ibm-pc at or compatible tb72k8 target board eva chip target application system figure 18-1 . smds product configuration (smds2+)
S3C72K8/p72k8 development tools 18- 3 tb72k8 target board the tb72k8 target board is used for the S3C72K8/p72k8 microcontroller. it is supported by the smds2+ development system. tb72k8 sm1247a 100-pin connector 25 1 reset to user_v cc off on j102 40-pin connector 2 1 39 40 + idle + stop 74hc11 u2 mds xi xtal j101 40-pin connector 2 1 39 40 mds xti xtal 144 qfp s3e72k0 eva chip figure 18-2 . tb72k8 target board configuration
development tools S3C72K8/p72k8) 18- 4 table 18-1. power selection settings for tb72k8 'to user_vcc' settings operating mode comments to user_v cc off on target system smds2/smds2+ tb72k8 v cc v ss v cc the smds2 /smds2+ supplies v cc to the target board (evaluation chip) and the target system. to user_v cc off on target system smds2/smds2+ tb72k8 external v cc v ss v cc the smds2 /smds2+ supplies v cc only to the target board (evaluation chip). the target system must have its own power supply. table 18-2. main-clock selection settings for tb72k8 sub clock setting operating mode comments xi mds xtal no connection smds2/smds2+ 100 pin connector eva chip s3e72k0 x in x out set the xi switch to ?mds? when the target board is connected to the smds2/smds2+. xi mds xtal target board eva chip s3e72k0 x in x out xtal set the xi switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+.
S3C72K8/p72k8 development tools 18- 5 table 18-3. sub-clock selection settings for tb72k8 sub clock setting operating mode comments xti mds xtal no connection smds2/smds2+ 100 pin connector eva chip s3e72k0 xt in xt out set the xti switch to ?mds? when the target board is connected to the smds2/smds2+. xti mds xtal target board eva chip s3e72k0 xt in xt out xtal set the xti switch to ?xtal? when the target board is used as a standalone unit, and is not connected to the smds2/smds2+. idle led this led is on when the evaluation chip ( s3e72k0 ) is in idle mode. stop led this led is on when the evaluation chip ( s3e72k0 ) is in stop mode.
development tools S3C72K8/p72k8) 18- 6 j102 com6 seg0 seg2 seg4 seg6 seg8 seg10 seg12 seg14 seg16 seg18 seg20 seg22 seg24 seg26 seg28 seg30 seg32/p5.0 seg34/p5.2 seg36/p5.4 com7 seg1 seg3 seg5 seg7 seg9 seg11 seg13 seg15 seg17 seg19 seg21 seg23 seg25 seg27 seg29 seg31 seg33/p5.1 seg35/p5.3 seg37/p5.5 j101 p5.6/seg38 v lc1 v lc3 v lc5 p0.1/so/k1 p0.3/buz/k3 v ss x in xt in reset p1.1/int1/cin1 p1.3/int4 p2.1 p2.3 p3.1 lcdck/p3.3 p4.1/tcl0 com0 com2 com4 p5.7/seg39 v lc2 v lc4 p0.0/ sck /k0 p0.2/si/k2 v dd x out test xt out p1.0/int0/cin0 p1.2/int2 p2.0 p2.2 p3.0 lcdsy/p3.2 p4.0/clo p4.2/tclo0 com1 com3 com5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 40-pin dip connector 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 40-pin dip connector 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 figure 18-3 . 40 -pin connector s for tb72k8 target board 40-pin dip connector target system 40-pin dip connector j102 1 2 39 40 j101 1 2 39 40 target cable for 40-pin connector part name: (as64d-a) order cods: sm6309 j102 1 2 39 40 j101 1 2 39 40 figure 18-4 . tb72k8 adapter cable for 80-qfp package ( S3C72K8/p72k8 )

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